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Merge pull request #1736 from rowanG077/buf-endpoint-cfg 

soc/interconnect/stream: BufferizeEndpoints params
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enjoy-digital 2023-08-28 15:58:46 +02:00 committed by GitHub
parent f7b35f09ae 91e1e53662
commit 8efcc4fdea
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1 changed files with 10 additions and 3 deletions
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13
litex/soc/interconnect/stream.py
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@ -985,7 +985,7 @@ class Pipeline(Module):
# Add buffers on Endpoints (can be used to improve timings) # Add buffers on Endpoints (can be used to improve timings)
class BufferizeEndpoints(ModuleTransformer): class BufferizeEndpoints(ModuleTransformer):
def __init__(self, endpoint_dict): def __init__(self, endpoint_dict, pipe_valid=True, pipe_ready=False):
self.endpoint_dict = endpoint_dict self.endpoint_dict = endpoint_dict
def transform_instance(self, submodule): def transform_instance(self, submodule):
@ -993,13 +993,20 @@ class BufferizeEndpoints(ModuleTransformer):
endpoint = getattr(submodule, name) endpoint = getattr(submodule, name)
# add buffer on sinks # add buffer on sinks
if direction == DIR_SINK: if direction == DIR_SINK:
buf = Buffer(endpoint.description) buf = Buffer(
endpoint.description,
pipe_valid=pipe_valid,
pipe_ready=pipe_ready
)
submodule.submodules += buf submodule.submodules += buf
setattr(submodule, name, buf.sink) setattr(submodule, name, buf.sink)
submodule.comb += buf.source.connect(endpoint) submodule.comb += buf.source.connect(endpoint)
# add buffer on sources # add buffer on sources
elif direction == DIR_SOURCE: elif direction == DIR_SOURCE:
buf = Buffer(endpoint.description) buf = Buffer(endpoint.description,
pipe_valid=pipe_valid,
pipe_ready=pipe_ready
)
submodule.submodules += buf submodule.submodules += buf
submodule.comb += endpoint.connect(buf.sink) submodule.comb += endpoint.connect(buf.sink)
setattr(submodule, name, buf.source) setattr(submodule, name, buf.source)