crg: support VGA pixel clock reprogramming
This commit is contained in:
Sebastien Bourdeauducq
parent
1e860c7472
commit
8fd092ca12
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@ -3,8 +3,9 @@ from fractions import Fraction
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from migen.fhdl.structure import *
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from migen.fhdl.specials import Instance
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from migen.fhdl.module import Module
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from migen.bank.description import *
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class M1CRG(Module):
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class M1CRG(Module, AutoReg):
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def __init__(self, pads, outfreq1x):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys2x_270 = ClockDomain()
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@ -17,12 +18,22 @@ class M1CRG(Module):
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self.clk4x_wr_strb = Signal()
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self.clk4x_rd_strb = Signal()
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self._r_cmd_data = RegisterField(10)
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self._r_send_cmd_data = RegisterRaw()
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self._r_send_go = RegisterRaw()
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self._r_status = RegisterField(3, READ_ONLY, WRITE_ONLY)
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###
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infreq = 50*1000000
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ratio = Fraction(outfreq1x)/Fraction(infreq)
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in_period = float(Fraction(1000000000)/Fraction(infreq))
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vga_progdata = Signal()
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vga_progen = Signal()
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vga_progdone = Signal()
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vga_locked = Signal()
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self.specials += Instance("m1crg",
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Instance.Parameter("in_period", in_period),
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Instance.Parameter("f_mult", ratio.numerator),
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@ -48,4 +59,40 @@ class M1CRG(Module):
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Instance.Output("ddr_clk_pad_p", pads.ddr_clk_p),
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Instance.Output("ddr_clk_pad_n", pads.ddr_clk_n),
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Instance.Output("eth_phy_clk_pad", pads.eth_phy_clk),
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Instance.Output("vga_clk_pad", pads.vga_clk))
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Instance.Output("vga_clk_pad", pads.vga_clk),
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Instance.Input("vga_progclk", ClockSignal()),
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Instance.Input("vga_progdata", vga_progdata),
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Instance.Input("vga_progen", vga_progen),
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Instance.Output("vga_progdone", vga_progdone),
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Instance.Output("vga_locked", vga_locked))
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remaining_bits = Signal(max=11)
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transmitting = Signal()
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self.comb += transmitting.eq(remaining_bits != 0)
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sr = Signal(10)
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self.sync += [
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If(self._r_send_cmd_data.re,
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remaining_bits.eq(10),
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sr.eq(self._r_cmd_data.field.r)
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).Elif(transmitting,
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remaining_bits.eq(remaining_bits - 1),
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sr.eq(sr[1:])
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)
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]
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self.comb += [
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vga_progdata.eq(transmitting & sr[0]),
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vga_progen.eq(transmitting | self._r_send_go.re)
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]
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# enforce gap between commands
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busy_counter = Signal(max=14)
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busy = Signal()
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self.comb += busy.eq(busy_counter != 0)
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self.sync += If(self._r_send_cmd_data.re,
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busy_counter.eq(13)
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).Elif(busy,
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busy_counter.eq(busy_counter - 1)
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)
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self.comb += self._r_status.field.w.eq(Cat(busy, vga_progdone, vga_locked))
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@ -18,4 +18,8 @@
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#define MINIMAC_EV_RX1 0x2
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#define MINIMAC_EV_TX 0x4
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#define CLKGEN_STATUS_BUSY 0x1
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#define CLKGEN_STATUS_PROGDONE 0x2
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#define CLKGEN_STATUS_LOCKED 0x4
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#endif /* __HW_FLAGS_H */
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25
top.py
25
top.py
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@ -65,17 +65,18 @@ class M1ClockPads:
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class SoC(Module):
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csr_base = 0xe0000000
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csr_map = {
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"uart": 0,
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"dfii": 1,
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"identifier": 2,
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"timer0": 3,
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"minimac": 4,
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"fb": 5,
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"asmiprobe": 6,
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"dvisampler0": 7,
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"dvisampler0_edid_mem": 8,
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"dvisampler1": 9,
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"dvisampler1_edid_mem": 10,
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"crg": 0,
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"uart": 1,
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"dfii": 2,
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"identifier": 3,
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"timer0": 4,
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"minimac": 5,
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"fb": 6,
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"asmiprobe": 7,
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"dvisampler0": 8,
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"dvisampler0_edid_mem": 9,
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"dvisampler1": 10,
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"dvisampler1_edid_mem": 11,
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}
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interrupt_map = {
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@ -134,6 +135,7 @@ class SoC(Module):
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#
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# CSR
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#
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self.submodules.crg = m1crg.M1CRG(M1ClockPads(platform), clk_freq)
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self.submodules.uart = uart.UART(platform.request("serial"), clk_freq, baud=115200)
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self.submodules.identifier = identifier.Identifier(0x4D31, version, int(clk_freq))
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self.submodules.timer0 = timer.Timer()
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@ -155,7 +157,6 @@ class SoC(Module):
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#
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# Clocking
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#
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self.submodules.crg = m1crg.M1CRG(M1ClockPads(platform), clk_freq)
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self.comb += [
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self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
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self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb)
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@ -33,7 +33,14 @@ module m1crg #(
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/* VGA clock */
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output vga_clk, /* < buffered, to internal clock network */
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output vga_clk_pad /* < forwarded through ODDR2, to I/O */
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output vga_clk_pad, /* < forwarded through ODDR2, to I/O */
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/* VGA clock control */
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input vga_progclk,
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input vga_progdata,
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input vga_progen,
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output vga_progdone,
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output vga_locked
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);
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/*
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@ -257,7 +264,6 @@ assign eth_tx_clk = eth_tx_clk_pad;
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* VGA clock
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*/
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// TODO: hook up the reprogramming interface
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DCM_CLKGEN #(
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.CLKFXDV_DIVIDE(2),
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.CLKFX_DIVIDE(4),
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@ -270,15 +276,15 @@ DCM_CLKGEN #(
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.CLKFX(vga_clk),
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.CLKFX180(),
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.CLKFXDV(),
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.LOCKED(),
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.PROGDONE(),
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.STATUS(),
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.CLKIN(pllout4),
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.FREEZEDCM(1'b0),
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.PROGCLK(1'b0),
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.PROGDATA(),
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.PROGEN(1'b0),
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.RST(1'b0)
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.PROGCLK(vga_progclk),
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.PROGDATA(vga_progdata),
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.PROGEN(vga_progen),
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.PROGDONE(vga_progdone),
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.LOCKED(vga_locked),
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.RST(~pll_lckd)
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);
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ODDR2 #(
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