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cores/gpio/GPIOTristate: Allow passing platform resource with subsignals directly.

This commit is contained in:
Florent Kermarrec 2021-11-30 15:32:48 +01:00
parent aebef65932
commit 9036050364
1 changed files with 8 additions and 3 deletions
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11
litex/soc/cores/gpio.py
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@ -73,8 +73,8 @@ class GPIOInOut(Module):
class GPIOTristate(_GPIOIRQ, Module, AutoCSR): class GPIOTristate(_GPIOIRQ, Module, AutoCSR):
def __init__(self, pads, with_irq=False): def __init__(self, pads, with_irq=False):
assert isinstance(pads, Signal) or isinstance(pads, Record) internal = not (hasattr(pads, "o") and hasattr(pads, "oe") and hasattr(pads, "i"))
nbits = len(pads) if isinstance(pads, Signal) else len(pads.o) nbits = len(pads) if internal else len(pads.o)
self._oe = CSRStorage(nbits, description="GPIO Tristate(s) Control.") self._oe = CSRStorage(nbits, description="GPIO Tristate(s) Control.")
self._in = CSRStatus(nbits, description="GPIO Input(s) Status.") self._in = CSRStatus(nbits, description="GPIO Input(s) Status.")
@ -82,7 +82,10 @@ class GPIOTristate(_GPIOIRQ, Module, AutoCSR):
# # # # # #
if isinstance(pads, Signal): # Internal Tristate.
if internal:
if isinstance(pads, Record):
pads = pads.raw_bits()
# Proper inout IOs. # Proper inout IOs.
for i in range(nbits): for i in range(nbits):
t = TSTriple() t = TSTriple()
@ -90,6 +93,8 @@ class GPIOTristate(_GPIOIRQ, Module, AutoCSR):
self.comb += t.oe.eq(self._oe.storage[i]) self.comb += t.oe.eq(self._oe.storage[i])
self.comb += t.o.eq(self._out.storage[i]) self.comb += t.o.eq(self._out.storage[i])
self.specials += MultiReg(t.i, self._in.status[i]) self.specials += MultiReg(t.i, self._in.status[i])
# External Tristate.
else: else:
# Tristate inout IOs (For external tristate IO chips or simulation). # Tristate inout IOs (For external tristate IO chips or simulation).
for i in range(nbits): for i in range(nbits):