Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity

integration/soc: add clock_domain parameter to add_etherbone.

Browse source 
To allow using a sys_clk < 125MHz with a 1Gbps link.
This commit is contained in:
Florent Kermarrec 2020-05-08 13:15:44 +02:00
parent f1a50a2138
commit 90c485fcc8
1 changed files with 14 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

16
litex/soc/integration/soc.py
View file

@ -1138,7 +1138,7 @@ class LiteXSoC(SoC):
eth_tx_clk)
# Add Etherbone --------------------------------------------------------------------------------
def add_etherbone(self, name="etherbone", phy=None,
def add_etherbone(self, name="etherbone", phy=None, clock_domain=None,
mac_address = 0x10e2d5000000,
ip_address = "192.168.1.50",
udp_port = 1234):
@ -1151,9 +1151,21 @@ class LiteXSoC(SoC):
mac_address = mac_address,
ip_address = ip_address,
clk_freq = self.clk_freq)
if clock_domain is not None: # FIXME: Could probably be avoided.
ethcore = ClockDomainsRenamer("eth_tx")(ethcore)
self.submodules += ethcore
# Clock domain renaming
if clock_domain is not None: # FIXME: Could probably be avoided.
self.clock_domains.cd_etherbone = ClockDomain("etherbone")
self.comb += self.cd_etherbone.clk.eq(ClockSignal(clock_domain))
self.comb += self.cd_etherbone.rst.eq(ResetSignal(clock_domain))
clock_domain = "etherbone"
else:
clock_domain = "sys"
# Etherbone
etherbone = LiteEthEtherbone(ethcore.udp, udp_port)
etherbone = LiteEthEtherbone(ethcore.udp, udp_port, cd=clock_domain)
setattr(self.submodules, name, etherbone)
self.add_wb_master(etherbone.wishbone.bus)
# Timing constraints