snyc
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@ -50,9 +50,11 @@ class VexiiRiscv(CPU):
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l2_bytes = 0
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l2_bytes = 0
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l2_ways = 4
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l2_ways = 4
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l2_self_flush = None
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l2_self_flush = None
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with_fpu = False
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with_rvc = False
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with_rvc = False
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with_rvm = False
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with_rvm = False
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with_rvf = False
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with_rvd = False
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with_rva = False
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with_dma = False
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with_dma = False
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jtag_tap = False
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jtag_tap = False
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jtag_instruction = False
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jtag_instruction = False
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@ -63,8 +65,10 @@ class VexiiRiscv(CPU):
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@staticmethod
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@staticmethod
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def get_abi():
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def get_abi():
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abi = "lp64" if VexiiRiscv.xlen == 64 else "ilp32"
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abi = "lp64" if VexiiRiscv.xlen == 64 else "ilp32"
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if VexiiRiscv.with_fpu:
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if VexiiRiscv.with_rvd:
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abi +="d"
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abi +="d"
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elif VexiiRiscv.with_rvf:
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abi +="f"
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return abi
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return abi
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# Arch.
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# Arch.
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@ -73,11 +77,19 @@ class VexiiRiscv(CPU):
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arch = f"rv{VexiiRiscv.xlen}i2p0_"
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arch = f"rv{VexiiRiscv.xlen}i2p0_"
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if VexiiRiscv.with_rvm:
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if VexiiRiscv.with_rvm:
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arch += "m"
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arch += "m"
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if VexiiRiscv.with_rva:
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arch += "a"
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arch += "a"
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if VexiiRiscv.with_fpu:
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if VexiiRiscv.with_rvf:
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arch += "fd"
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arch += "f"
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if VexiiRiscv.with_rvd:
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arch += "d"
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if VexiiRiscv.with_rvc:
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if VexiiRiscv.with_rvc:
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arch += "c"
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arch += "c"
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# arch += "zicntr"
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# arch += "zicsr"
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# arch += "zifencei"
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# arch += "zihpm"
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# arch += "sscofpmf"
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return arch
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return arch
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# Memory Mapping.
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# Memory Mapping.
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@ -134,7 +146,7 @@ class VexiiRiscv(CPU):
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vdir = get_data_mod("cpu", "vexiiriscv").data_location
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vdir = get_data_mod("cpu", "vexiiriscv").data_location
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ndir = os.path.join(vdir, "ext", "VexiiRiscv")
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ndir = os.path.join(vdir, "ext", "VexiiRiscv")
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NaxRiscv.git_setup("VexiiRiscv", ndir, "https://github.com/SpinalHDL/VexiiRiscv.git", "dev", "0ec757d2", args.update_repo)
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NaxRiscv.git_setup("VexiiRiscv", ndir, "https://github.com/SpinalHDL/VexiiRiscv.git", "dev", "61ed758d", args.update_repo)
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if not args.cpu_variant:
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if not args.cpu_variant:
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args.cpu_variant = "standard"
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args.cpu_variant = "standard"
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@ -341,10 +353,6 @@ class VexiiRiscv(CPU):
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gen_args.append(f"--with-jtag-instruction")
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gen_args.append(f"--with-jtag-instruction")
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if(VexiiRiscv.with_dma) :
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if(VexiiRiscv.with_dma) :
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gen_args.append(f"--with-dma")
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gen_args.append(f"--with-dma")
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# if(VexiiRiscv.with_fpu):
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# gen_args.append(f"--scala-args=rvf=true,rvd=true")
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# if(VexiiRiscv.with_rvc):
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# gen_args.append(f"--scala-args=rvc=true")
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cmd = f"""cd {ndir} && sbt "runMain vexiiriscv.soc.litex.SocGen {" ".join(gen_args)}\""""
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cmd = f"""cd {ndir} && sbt "runMain vexiiriscv.soc.litex.SocGen {" ".join(gen_args)}\""""
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print("VexiiRiscv generation command :")
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print("VexiiRiscv generation command :")
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