remove genlib.misc.optree (use reduce instead)

This commit is contained in:
Sebastien Bourdeauducq 2015-09-10 13:56:56 -07:00
parent 1dcd2ac1c0
commit 91ab3f0d01
4 changed files with 13 additions and 28 deletions

View File

@ -1,6 +1,8 @@
from migen.fhdl.std import *
from migen.fhdl import verilog
from migen.genlib.misc import optree
from functools import reduce
from operator import or_
def gen_list(n):
@ -37,6 +39,6 @@ class Example(Module):
for lst in [a, b, c]:
for obj in lst:
allsigs.extend(obj.sigs)
self.comb += output.eq(optree("|", allsigs))
self.comb += output.eq(reduce(or_, allsigs))
print(verilog.convert(Example()))

View File

@ -4,9 +4,10 @@ import matplotlib.pyplot as plt
from migen.fhdl.std import *
from migen.fhdl import verilog
from migen.genlib.misc import optree
from migen.sim.generic import run_simulation
from functools import reduce
from operator import add
# A synthesizable FIR filter.
class FIR(Module):
@ -27,7 +28,7 @@ class FIR(Module):
c_fp = int(c*2**(self.wsize - 1))
muls.append(c_fp*sreg)
sum_full = Signal((2*self.wsize-1, True))
self.sync += sum_full.eq(optree("+", muls))
self.sync += sum_full.eq(reduce(add, muls))
self.comb += self.o.eq(sum_full[self.wsize-1:])

View File

@ -1,25 +1,4 @@
from migen.fhdl.std import *
from migen.fhdl.structure import _Operator
def optree(op, operands, lb=None, ub=None, default=None):
if lb is None:
lb = 0
if ub is None:
ub = len(operands)
l = ub - lb
if l == 0:
if default is None:
raise AttributeError
else:
return default
elif l == 1:
return operands[lb]
else:
s = lb + l//2
return _Operator(op,
[optree(op, operands, lb, s, default),
optree(op, operands, s, ub, default)])
def split(v, *counts):

View File

@ -1,6 +1,9 @@
from migen.fhdl.std import *
from migen.fhdl.tracer import get_obj_var_name
from migen.genlib.misc import optree
from functools import reduce
from operator import or_
(DIR_NONE, DIR_S_TO_M, DIR_M_TO_S) = range(3)
@ -141,7 +144,7 @@ class Record:
if direction == DIR_M_TO_S:
r += [getattr(slave, field).eq(self_e) for slave in slaves]
elif direction == DIR_S_TO_M:
r.append(self_e.eq(optree("|", [getattr(slave, field) for slave in slaves])))
r.append(self_e.eq(reduce(or_, [getattr(slave, field) for slave in slaves])))
else:
raise TypeError
else:
@ -164,7 +167,7 @@ class Record:
s_signal, s_direction = next(iter_slave)
assert(s_direction == DIR_S_TO_M)
s_signals.append(s_signal)
r.append(m_signal.eq(optree("|", s_signals)))
r.append(m_signal.eq(reduce(or_, s_signals)))
else:
raise TypeError
return r