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cpu/microwatt: Set XICS_ICS's SRC_NUM to 16. 

Expected to be 16 in xics.vhdl: assert SRC_NUM = 16 report "Fixup address decode with log2";
This commit is contained in:
Florent Kermarrec 2021-02-22 10:57:31 +01:00
parent a51bf60712
commit 91cebb5159
1 changed files with 2 additions and 18 deletions
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20
litex/soc/cores/cpu/microwatt/xics_wrapper.vhdl
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@ -108,7 +108,7 @@ architecture rtl of xics_ics_wrapper is
signal wishbone_out : wb_io_slave_out;
signal icp_out : ics_to_icp_t;
signal int_level_uw : std_ulogic_vector(255 downto 0);
signal int_level_uw : std_ulogic_vector(15 downto 0);
begin
-- wishbone mapping
@ -146,27 +146,11 @@ begin
int_level_uw(13) <= int_level_in(13);
int_level_uw(14) <= int_level_in(14);
int_level_uw(15) <= int_level_in(15);
int_level_uw(16) <= int_level_in(16);
int_level_uw(17) <= int_level_in(17);
int_level_uw(18) <= int_level_in(18);
int_level_uw(19) <= int_level_in(19);
int_level_uw(20) <= int_level_in(20);
int_level_uw(21) <= int_level_in(21);
int_level_uw(22) <= int_level_in(22);
int_level_uw(23) <= int_level_in(23);
int_level_uw(24) <= int_level_in(24);
int_level_uw(25) <= int_level_in(25);
int_level_uw(26) <= int_level_in(26);
int_level_uw(27) <= int_level_in(27);
int_level_uw(28) <= int_level_in(28);
int_level_uw(29) <= int_level_in(29);
int_level_uw(30) <= int_level_in(30);
int_level_uw(31) <= int_level_in(31);
end process;
xics_ics : entity work.xics_ics
generic map (
SRC_NUM => 256
SRC_NUM => 16
)
port map (
clk => clk,