cpu/vexriscv: Redo csr instruction fix
Instead of enabling the zicsr extension in crt0.S, change -march to specify that VexRISCV implements version 2.0 of I, rather than the latest (2.1). In 2.0 the csr instructions were still part of I. This approach has two advantages: * It is compatible with older versions of binutils, since they do not need to know about the new zicsr extension * By modifying the -march in CFLAGS, csr instructions can be used in any code (for example by the inline functions in irq.h), not just in crt0.S.
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@ -46,30 +46,30 @@ CPU_VARIANTS = {
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# GCC Flags ----------------------------------------------------------------------------------------
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# GCC Flags ----------------------------------------------------------------------------------------
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GCC_FLAGS = {
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GCC_FLAGS = {
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# /-------- Base ISA
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# /---------- Base ISA
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# |/------- Hardware Multiply + Divide
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# | /----- Hardware Multiply + Divide
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# ||/----- Atomics
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# | |/---- Atomics
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# |||/---- Compressed ISA
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# | ||/--- Compressed ISA
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# ||||/--- Single-Precision Floating-Point
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# | |||/-- Single-Precision Floating-Point
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# |||||/-- Double-Precision Floating-Point
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# | ||||/- Double-Precision Floating-Point
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# i macfd
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# i macfd
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"minimal": "-march=rv32i -mabi=ilp32",
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"minimal": "-march=rv32i2p0 -mabi=ilp32",
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"minimal+debug": "-march=rv32i -mabi=ilp32",
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"minimal+debug": "-march=rv32i2p0 -mabi=ilp32",
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"lite": "-march=rv32im -mabi=ilp32",
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"lite": "-march=rv32i2p0_m -mabi=ilp32",
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"lite+debug": "-march=rv32im -mabi=ilp32",
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"lite+debug": "-march=rv32i2p0_m -mabi=ilp32",
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"standard": "-march=rv32im -mabi=ilp32",
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"standard": "-march=rv32i2p0_m -mabi=ilp32",
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"standard+debug": "-march=rv32im -mabi=ilp32",
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"standard+debug": "-march=rv32i2p0_m -mabi=ilp32",
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"imac": "-march=rv32imac -mabi=ilp32",
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"imac": "-march=rv32i2p0_mac -mabi=ilp32",
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"imac+debug": "-march=rv32imac -mabi=ilp32",
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"imac+debug": "-march=rv32i2p0_mac -mabi=ilp32",
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"full": "-march=rv32im -mabi=ilp32",
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"full": "-march=rv32i2p0_m -mabi=ilp32",
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"full+cfu": "-march=rv32im -mabi=ilp32",
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"full+cfu": "-march=rv32i2p0_m -mabi=ilp32",
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"full+debug": "-march=rv32im -mabi=ilp32",
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"full+debug": "-march=rv32i2p0_m -mabi=ilp32",
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"full+cfu+debug": "-march=rv32im -mabi=ilp32",
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"full+cfu+debug": "-march=rv32i2p0_m -mabi=ilp32",
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"linux": "-march=rv32ima -mabi=ilp32",
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"linux": "-march=rv32i2p0_ma -mabi=ilp32",
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"linux+debug": "-march=rv32ima -mabi=ilp32",
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"linux+debug": "-march=rv32i2p0_ma -mabi=ilp32",
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"linux+no-dsp": "-march=rv32ima -mabi=ilp32",
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"linux+no-dsp": "-march=rv32i2p0_ma -mabi=ilp32",
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"secure": "-march=rv32ima -mabi=ilp32",
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"secure": "-march=rv32i2p0_ma -mabi=ilp32",
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"secure+debug": "-march=rv32ima -mabi=ilp32",
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"secure+debug": "-march=rv32i2p0_ma -mabi=ilp32",
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}
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}
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# VexRiscv Timer -----------------------------------------------------------------------------------
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# VexRiscv Timer -----------------------------------------------------------------------------------
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@ -2,8 +2,6 @@
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.global isr
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.global isr
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.global _start
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.global _start
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.option arch,+zicsr
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_start:
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_start:
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j crt_init
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j crt_init
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nop
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nop
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@ -120,7 +120,7 @@ class VexRiscvSMP(CPU):
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# Arch.
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# Arch.
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@staticmethod
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@staticmethod
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def get_arch():
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def get_arch():
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arch = "rv32ima"
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arch = "rv32i2p0_ma"
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if VexRiscvSMP.with_fpu:
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if VexRiscvSMP.with_fpu:
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arch += "fd"
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arch += "fd"
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if VexRiscvSMP.with_rvc:
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if VexRiscvSMP.with_rvc:
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@ -7,8 +7,6 @@
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.global smp_lottery_args
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.global smp_lottery_args
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.global smp_slave
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.global smp_slave
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.option arch,+zicsr
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_start:
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_start:
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j crt_init
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j crt_init
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nop
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nop
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