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mibuild/xilinx/ise: update synthesis with yosis

This commit is contained in:
Florent Kermarrec 2015-08-19 01:09:54 +02:00
parent 646667213e
commit 9210df9e9f
1 changed files with 2 additions and 14 deletions
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16
mibuild/xilinx/ise.py
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@ -69,24 +69,12 @@ def _run_yosys(device, sources, vincpaths, build_name):
incflags = ""
for path in vincpaths:
incflags += " -I" + path
for filename, language in sources:
for filename, language, library in sources:
ys_contents += "read_{}{} {}\n".format(language, incflags, filename)
if device[:2] == "xc":
archcode = device[2:4]
else:
archcode = device[0:2]
arch = {
"6s": "spartan6",
"7a": "artix7",
"7k": "kintex7",
"7v": "virtex7",
"7z": "zynq7000"
}[archcode]
ys_contents += """hierarchy -check -top top
proc; memory; opt; fsm; opt
synth_xilinx -arch {arch} -top top -edif {build_name}.edif""".format(arch=arch, build_name=build_name)
synth_xilinx -top top -edif {build_name}.edif""".format(build_name=build_name)
ys_name = build_name + ".ys"
tools.write_to_file(ys_name, ys_contents)