Merge pull request #1171 from enjoy-digital/out-of-tree-cpus
Simplify CPUs collection and add out-of-tree support.
This commit is contained in:
enjoy-digital
GitHub
commit
928ee285dc
2
CHANGES
2
CHANGES
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@ -20,11 +20,13 @@
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- cpu/eos_s3: Add LiteX BIOS/Bare Metal software support.
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- litex_sim: Add .json support for --rom/ram/sdram-init.
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- soc/add_uart: Allow multiple UARTs in the same design.
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- cores/cpu: Add out-of-tree support.
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[> API changes/Deprecation
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--------------------------
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- Fully deprecate SoCSDRAM/SPIFlash core (replaced by LiteSPI).
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- UART "bridge" name deprecated in favor of "crossover" (already supported).
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- "external" CPU class support deprecated (replaced by out-of-tree support).
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[> 2021.12, released on January 5th 2022
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----------------------------------------
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@ -1,10 +1,15 @@
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#
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# This file is part of LiteX.
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#
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# Copyright (c) 2015-2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2015-2022 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2017-2018 Tim 'mithro' Ansell <me@mith.ro>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import sys
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import inspect
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import importlib
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from migen import *
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# CPU ----------------------------------------------------------------------------------------------
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@ -43,21 +48,6 @@ class CPUNone(CPU):
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"spiflash" : 0x10000000, # FIXME: Remove.
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}
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CPU_GCC_TRIPLE_RISCV32 = (
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"riscv64-unknown-elf",
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"riscv64-unknown-linux-gnu",
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"riscv32-unknown-elf",
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"riscv32-unknown-linux-gnu",
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"riscv64-elf",
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"riscv32-elf",
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"riscv-none-embed",
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"riscv-none-elf",
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"riscv64-linux",
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"riscv64-linux-gnu",
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"riscv-sifive-elf",
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"riscv64-none-elf",
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)
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CPU_GCC_TRIPLE_RISCV64 = (
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"riscv64-unknown-elf",
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"riscv64-unknown-linux-gnu",
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@ -68,78 +58,50 @@ CPU_GCC_TRIPLE_RISCV64 = (
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"riscv64-none-elf",
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)
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CPU_GCC_TRIPLE_RISCV32 = CPU_GCC_TRIPLE_RISCV64 + (
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"riscv32-unknown-elf",
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"riscv32-unknown-linux-gnu",
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"riscv32-elf",
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"riscv-none-embed",
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"riscv-none-elf",
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)
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# CPUS ---------------------------------------------------------------------------------------------
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# LM32
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from litex.soc.cores.cpu.lm32 import LM32
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def collect_cpus():
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cpus = {"None" : CPUNone}
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paths = [
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# Add litex.soc.cores.cpu path.
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os.path.dirname(__file__),
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# Add execution path.
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os.getcwd()
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]
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# OpenRisc
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from litex.soc.cores.cpu.mor1kx import MOR1KX
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from litex.soc.cores.cpu.marocchino import Marocchino
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exec_dir = os.getcwd()
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# OpenPower
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from litex.soc.cores.cpu.microwatt import Microwatt
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# Search for CPUs in paths.
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for path in paths:
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for file in os.listdir(path):
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# RISC-V (32-bit)
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from litex.soc.cores.cpu.serv import SERV
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from litex.soc.cores.cpu.femtorv import FemtoRV
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from litex.soc.cores.cpu.picorv32 import PicoRV32
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from litex.soc.cores.cpu.minerva import Minerva
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from litex.soc.cores.cpu.vexriscv import VexRiscv
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from litex.soc.cores.cpu.vexriscv_smp import VexRiscvSMP
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from litex.soc.cores.cpu.ibex import Ibex
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from litex.soc.cores.cpu.cv32e40p import CV32E40P
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# Verify that it's a path...
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cpu_path = os.path.join(path, file)
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if not os.path.isdir(cpu_path):
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continue
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# RISC-V (64-bit)
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from litex.soc.cores.cpu.rocket import RocketRV64
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from litex.soc.cores.cpu.blackparrot import BlackParrotRV64
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# ... and that core.py is present.
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cpu_core = os.path.join(cpu_path, "core.py")
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if not os.path.exists(cpu_core):
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continue
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# Zynq
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from litex.soc.cores.cpu.zynq7000 import Zynq7000
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# OK, it seems to be a CPU; now get the class and add it to dict.
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cpu = file
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cpu_module = f"{cpu}"
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sys.path.append(path)
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for cpu_name, cpu_cls in inspect.getmembers(importlib.import_module(cpu_module), inspect.isclass):
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if cpu.replace("_", "") == cpu_name.lower():
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cpus[cpu] = cpu_cls
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# EOS-S3
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from litex.soc.cores.cpu.eos_s3 import EOS_S3
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# Return collected CPUs.
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return cpus
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# Gowin EMCU
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from litex.soc.cores.cpu.gowin_emcu import GowinEMCU
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CPUS = {
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# None
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"None" : CPUNone,
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# External (CPU class provided externally by design/user)
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"external" : None,
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# LM32
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"lm32" : LM32,
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# OpenRisc
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"mor1kx" : MOR1KX,
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"marocchino" : Marocchino,
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# OpenPower
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"microwatt" : Microwatt,
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# RISC-V (32-bit)
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"serv" : SERV,
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"femtorv" : FemtoRV,
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"picorv32" : PicoRV32,
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"minerva" : Minerva,
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"vexriscv" : VexRiscv,
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"vexriscv_smp": VexRiscvSMP,
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"ibex" : Ibex,
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"cv32e40p" : CV32E40P,
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# RISC-V (64-bit)
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"rocket" : RocketRV64,
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"blackparrot" : BlackParrotRV64,
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# Zynq
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"zynq7000" : Zynq7000,
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# EOS-S3
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"eos_s3" : EOS_S3,
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# Gowin EMCU
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'gowin_emcu' : GowinEMCU
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}
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CPUS = collect_cpus()
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@ -884,7 +884,7 @@ class SoC(Module):
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self.add_config("CSR_DATA_WIDTH", self.csr.data_width)
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self.add_config("CSR_ALIGNMENT", self.csr.alignment)
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def add_cpu(self, name="vexriscv", variant="standard", cls=None, reset_address=None, cfu=None):
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def add_cpu(self, name="vexriscv", variant="standard", reset_address=None, cfu=None):
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# Check that CPU is supported.
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if name not in cpu.CPUS.keys():
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self.logger.error("{} CPU {}, supporteds: {}.".format(
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@ -894,12 +894,7 @@ class SoC(Module):
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raise SoCError()
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# Add CPU.
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if name == "external" and cls is None:
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self.logger.error("{} CPU requires {} to be specified.".format(
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colorer(name),
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colorer("cpu_cls", color="red")))
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raise SoCError()
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cpu_cls = cls if cls is not None else cpu.CPUS[name]
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cpu_cls = cpu.CPUS[name]
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if (variant not in cpu_cls.variants) and (cpu_cls is not cpu.CPUNone):
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self.logger.error("{} CPU variant {}, supporteds: {}.".format(
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colorer(variant),
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@ -69,7 +69,6 @@ class SoCCore(LiteXSoC):
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cpu_type = "vexriscv",
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cpu_reset_address = None,
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cpu_variant = None,
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cpu_cls = None,
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cpu_cfu = None,
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# CFU parameters
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@ -149,7 +148,6 @@ class SoCCore(LiteXSoC):
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self.cpu_type = cpu_type
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self.cpu_variant = cpu_variant
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self.cpu_cls = cpu_cls
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# ROM.
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# Initialize ROM from binary file when provided.
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@ -187,7 +185,6 @@ class SoCCore(LiteXSoC):
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name = str(cpu_type),
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variant = "standard" if cpu_variant is None else cpu_variant,
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reset_address = None if integrated_rom_size else cpu_reset_address,
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cls = cpu_cls,
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cfu = cpu_cfu)
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# Add User's interrupts
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