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phy: add hw_init_reset (useful when used without CPU)

This commit is contained in:
Florent Kermarrec 2015-02-10 16:01:40 +01:00
parent 000ba7f0ab
commit 92904330f7
2 changed files with 28 additions and 8 deletions
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16
liteeth/phy/gmii.py
View File

@ -34,7 +34,7 @@ class LiteEthPHYGMIIRX(Module):
# CRG is the only Xilinx specific module.
# TODO: use generic code or add support for others vendors
class LiteEthPHYGMIICRG(Module, AutoCSR):
def __init__(self, clock_pads, pads):
def __init__(self, clock_pads, pads, with_hw_init_reset):
self._reset = CSRStorage()
###
self.clock_domains.cd_eth_rx = ClockDomain()
@ -49,6 +49,16 @@ class LiteEthPHYGMIICRG(Module, AutoCSR):
]
self.comb += self.cd_eth_tx.clk.eq(self.cd_eth_rx.clk)
if with_hw_init_reset:
reset = Signal()
counter_done = Signal()
self.submodules.counter = counter = Counter(max=512)
self.comb += [
counter_done.eq(counter.value == 256),
counter.ce.eq(~counter_done),
reset.eq(~counter_done | self._reset.storage)
]
else:
reset = self._reset.storage
self.comb += pads.rst_n.eq(~reset)
self.specials += [
@ -57,9 +67,9 @@ class LiteEthPHYGMIICRG(Module, AutoCSR):
]
class LiteEthPHYGMII(Module, AutoCSR):
def __init__(self, clock_pads, pads):
def __init__(self, clock_pads, pads, with_hw_init_reset=True):
self.dw = 8
self.submodules.crg = LiteEthPHYGMIICRG(clock_pads, pads)
self.submodules.crg = LiteEthPHYGMIICRG(clock_pads, pads, with_hw_init_reset)
self.submodules.tx = RenameClockDomains(LiteEthPHYGMIITX(pads), "eth_tx")
self.submodules.rx = RenameClockDomains(LiteEthPHYGMIIRX(pads), "eth_rx")
self.sink, self.source = self.tx.sink, self.rx.source

16
liteeth/phy/mii.py
View File

@ -90,7 +90,7 @@ class LiteEthPHYMIIRX(Module):
)
class LiteEthPHYMIICRG(Module, AutoCSR):
def __init__(self, clock_pads, pads):
def __init__(self, clock_pads, pads, with_hw_init_reset):
self._reset = CSRStorage()
###
self.sync.base50 += clock_pads.phy.eq(~clock_pads.phy)
@ -100,6 +100,16 @@ class LiteEthPHYMIICRG(Module, AutoCSR):
self.comb += self.cd_eth_rx.clk.eq(clock_pads.rx)
self.comb += self.cd_eth_tx.clk.eq(clock_pads.tx)
if with_hw_init_reset:
reset = Signal()
counter_done = Signal()
self.submodules.counter = counter = Counter(max=512)
self.comb += [
counter_done.eq(counter.value == 256),
counter.ce.eq(~counter_done),
reset.eq(~counter_done | self._reset.storage)
]
else:
reset = self._reset.storage
self.comb += pads.rst_n.eq(~reset)
self.specials += [
@ -108,9 +118,9 @@ class LiteEthPHYMIICRG(Module, AutoCSR):
]
class LiteEthPHYMII(Module, AutoCSR):
def __init__(self, clock_pads, pads):
def __init__(self, clock_pads, pads, with_hw_init_reset=True):
self.dw = 8
self.submodules.crg = LiteEthPHYMIICRG(clock_pads, pads)
self.submodules.crg = LiteEthPHYMIICRG(clock_pads, pads, with_hw_init_reset)
self.submodules.tx = RenameClockDomains(LiteEthPHYMIITX(pads), "eth_tx")
self.submodules.rx = RenameClockDomains(LiteEthPHYMIIRX(pads), "eth_rx")
self.sink, self.source = self.tx.sink, self.rx.source