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targets/arty: allow setting synth-mode to yosys with command line: --synth-mode=yosys

This commit is contained in:
Florent Kermarrec 2019-10-07 10:38:26 +02:00
parent 4a1cefe946
commit 92975b139e
1 changed files with 3 additions and 1 deletions
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4
litex/boards/targets/arty.py
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@ -8,6 +8,7 @@ import argparse
from migen import * from migen import *
from litex.boards.platforms import arty from litex.boards.platforms import arty
from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
from litex.soc.cores.clock import * from litex.soc.cores.clock import *
from litex.soc.integration.soc_sdram import * from litex.soc.integration.soc_sdram import *
@ -105,6 +106,7 @@ def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Arty") parser = argparse.ArgumentParser(description="LiteX SoC on Arty")
builder_args(parser) builder_args(parser)
soc_sdram_args(parser) soc_sdram_args(parser)
vivado_build_args(parser)
parser.add_argument("--with-ethernet", action="store_true", parser.add_argument("--with-ethernet", action="store_true",
help="enable Ethernet support") help="enable Ethernet support")
args = parser.parse_args() args = parser.parse_args()
@ -112,7 +114,7 @@ def main():
cls = EthernetSoC if args.with_ethernet else BaseSoC cls = EthernetSoC if args.with_ethernet else BaseSoC
soc = cls(**soc_sdram_argdict(args)) soc = cls(**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))
builder.build() builder.build(**vivado_build_argdict(args))
if __name__ == "__main__": if __name__ == "__main__":