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https://github.com/enjoy-digital/litex.git
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dfii: new design
This commit is contained in:
Sebastien Bourdeauducq
parent
b3ca952a39
commit
92ac69bae3
5 changed files with 176 additions and 117 deletions
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@ -3,26 +3,53 @@ from migen.bus import dfi
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from migen.bank.description import *
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from migen.bank import csrgen
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def _data_en(trigger, output, delay, duration):
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dcounter = Signal(BV(4))
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dce = Signal()
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return [
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If(trigger,
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dcounter.eq(delay),
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dce.eq(1)
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).Elif(dce,
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dcounter.eq(dcounter - 1),
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If(dcounter == 0,
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If(~output,
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output.eq(1),
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dcounter.eq(duration)
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class PhaseInjector:
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def __init__(self, phase):
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self.phase = phase
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self._cs = Field("cs", 1, WRITE_ONLY, READ_ONLY)
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self._we = Field("we", 1, WRITE_ONLY, READ_ONLY)
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self._cas = Field("cas", 1, WRITE_ONLY, READ_ONLY)
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self._ras = Field("ras", 1, WRITE_ONLY, READ_ONLY)
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self._wren = Field("wren", 1, WRITE_ONLY, READ_ONLY)
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self._rden = Field("rden", 1, WRITE_ONLY, READ_ONLY)
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self._command = RegisterFields("command",
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[self._cs, self._we, self._cas, self._ras, self._wren, self._rden])
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self._address = RegisterField("address", self.phase.address.bv.width)
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self._baddress = RegisterField("baddress", self.phase.bank.bv.width)
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self._wrdata = RegisterField("wrdata", self.phase.wrdata.bv.width)
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self._rddata = RegisterField("rddata", self.phase.rddata.bv.width, READ_ONLY, WRITE_ONLY)
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def get_registers(self):
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return [self._command,
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self._address, self._baddress,
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self._wrdata, self._rddata]
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def get_fragment(self):
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comb = [
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If(self._command.re,
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self.phase.cs_n.eq(~self._cs.r),
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self.phase.we_n.eq(~self._we.r),
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self.phase.cas_n.eq(~self._cas.r),
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self.phase.ras_n.eq(~self._ras.r)
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).Else(
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output.eq(0),
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dce.eq(0)
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)
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)
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)
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self.phase.cs_n.eq(1),
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self.phase.we_n.eq(1),
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self.phase.cas_n.eq(1),
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self.phase.ras_n.eq(1)
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),
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self.phase.address.eq(self._address.field.r),
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self.phase.bank.eq(self._baddress.field.r),
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self.phase.wrdata.eq(self._wrdata.field.r)
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]
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sync = [
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self.phase.wrdata_en.eq(self._command.re & self._wren.r),
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self.phase.rddata_en.eq(self._command.re & self._rden.r),
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If(self.phase.rddata_valid, self._rddata.field.w.eq(self.phase.rddata))
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]
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return Fragment(comb, sync)
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class DFIInjector:
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def __init__(self, csr_address, a, ba, d, nphases=1):
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@ -34,84 +61,19 @@ class DFIInjector:
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self._cke = Field("cke")
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self._control = RegisterFields("control", [self._sel, self._cke])
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self._cs = Field("cs", 1, WRITE_ONLY, READ_ONLY)
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self._we = Field("we", 1, WRITE_ONLY, READ_ONLY)
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self._cas = Field("cas", 1, WRITE_ONLY, READ_ONLY)
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self._ras = Field("ras", 1, WRITE_ONLY, READ_ONLY)
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self._rddata = Field("rddata", 1, WRITE_ONLY, READ_ONLY)
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self._wrdata = Field("wrdata", 1, WRITE_ONLY, READ_ONLY)
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self._command = RegisterFields("command",
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[self._cs, self._we, self._cas, self._ras, self._rddata, self._wrdata])
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self._phase_injectors = [PhaseInjector(phase) for phase in self._int.phases]
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self._address = RegisterField("address", a)
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self._baddress = RegisterField("baddress", ba)
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self._rddelay = RegisterField("rddelay", 4, reset=5)
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self._rdduration = RegisterField("rdduration", 3, reset=0)
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self._wrdelay = RegisterField("wrdelay", 4, reset=3)
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self._wrduration = RegisterField("wrduration", 3, reset=0)
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self.bank = csrgen.Bank([
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self._control, self._command,
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self._address, self._baddress,
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self._rddelay, self._rdduration,
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self._wrdelay, self._wrduration
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], address=csr_address)
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registers = sum([pi.get_registers() for pi in self._phase_injectors], [self._control])
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self.bank = csrgen.Bank(registers, address=csr_address)
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def get_fragment(self):
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comb = []
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sync = []
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# mux
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connect_int = dfi.interconnect_stmts(self._int, self.master)
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connect_slave = dfi.interconnect_stmts(self.slave, self.master)
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comb.append(If(self._sel.r, *connect_slave).Else(*connect_int))
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# phases
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rddata_en = Signal()
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wrdata_en = Signal()
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for phase in self._int.phases:
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comb += [
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phase.cke.eq(self._cke.r),
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phase.rddata_en.eq(rddata_en),
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phase.wrdata_en.eq(wrdata_en)
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]
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cmdphase = self._int.phases[0]
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for phase in self._int.phases[1:]:
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comb += [
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phase.cs_n.eq(1),
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phase.we_n.eq(1),
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phase.cas_n.eq(1),
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phase.ras_n.eq(1)
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comb = [
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If(self._sel.r, *connect_slave).Else(*connect_int)
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]
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comb += [phase.cke.eq(self._cke.r) for phase in self._int.phases]
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# commands
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comb += [
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If(self._command.re,
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cmdphase.cs_n.eq(~self._cs.r),
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cmdphase.we_n.eq(~self._we.r),
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cmdphase.cas_n.eq(~self._cas.r),
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cmdphase.ras_n.eq(~self._ras.r)
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).Else(
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cmdphase.cs_n.eq(1),
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cmdphase.we_n.eq(1),
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cmdphase.cas_n.eq(1),
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cmdphase.ras_n.eq(1)
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)
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]
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# addresses
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comb += [
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cmdphase.address.eq(self._address.field.r),
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cmdphase.bank.eq(self._baddress.field.r)
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]
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# data enables
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sync += _data_en(self._command.re & self._rddata.r,
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rddata_en,
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self._rddelay.field.r, self._rdduration.field.r)
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sync += _data_en(self._command.re & self._wrdata.r,
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wrdata_en,
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self._wrdelay.field.r, self._wrduration.field.r)
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return Fragment(comb, sync) + self.bank.get_fragment()
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return Fragment(comb) \
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+ sum([pi.get_fragment() for pi in self._phase_injectors], Fragment()) \
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+ self.bank.get_fragment()
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@ -16,6 +16,7 @@
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <hw/dfii.h>
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@ -31,8 +32,10 @@ static void cdelay(int i)
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static void setaddr(int a)
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{
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CSR_DFII_AH = (a & 0x1fe0) >> 5;
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CSR_DFII_AL = a & 0x001f;
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CSR_DFII_AH_P0 = (a & 0x1fe0) >> 5;
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CSR_DFII_AL_P0 = a & 0x001f;
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CSR_DFII_AH_P1 = (a & 0x1fe0) >> 5;
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CSR_DFII_AL_P1 = a & 0x001f;
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}
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static void init_sequence(void)
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@ -43,46 +46,105 @@ static void init_sequence(void)
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/* Bring CKE high */
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setaddr(0x0000);
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CSR_DFII_BA = 0;
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CSR_DFII_BA_P0 = 0;
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CSR_DFII_CONTROL = DFII_CONTROL_CKE;
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/* Precharge All */
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setaddr(0x0400);
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CSR_DFII_COMMAND = DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS;
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CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS;
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/* Load Extended Mode Register */
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CSR_DFII_BA = 1;
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CSR_DFII_BA_P0 = 1;
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setaddr(0x0000);
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CSR_DFII_COMMAND = DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS;
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CSR_DFII_BA = 0;
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CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS;
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CSR_DFII_BA_P0 = 0;
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/* Load Mode Register */
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setaddr(0x0132); /* Reset DLL, CL=3, BL=4 */
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CSR_DFII_COMMAND = DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS;
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CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS;
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cdelay(200);
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/* Precharge All */
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setaddr(0x0400);
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CSR_DFII_COMMAND = DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS;
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CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS;
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/* 2x Auto Refresh */
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for(i=0;i<2;i++) {
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setaddr(0);
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CSR_DFII_COMMAND = DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_CS;
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CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_CS;
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cdelay(4);
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}
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/* Load Mode Register */
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setaddr(0x0032); /* CL=3, BL=4 */
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CSR_DFII_COMMAND = DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS;
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CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS;
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cdelay(200);
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}
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void ddrrd(char *startaddr)
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{
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char *c;
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unsigned int addr;
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int i;
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if(*startaddr == 0) {
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printf("ddrrd <address>\n");
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return;
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}
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addr = strtoul(startaddr, &c, 0);
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if(*c != 0) {
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printf("incorrect address\n");
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return;
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}
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setaddr(addr);
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CSR_DFII_BA_P0 = 0;
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CSR_DFII_COMMAND_P0 = DFII_COMMAND_CAS|DFII_COMMAND_CS|DFII_COMMAND_RDDATA;
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cdelay(15);
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for(i=0;i<8;i++)
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printf("%08x ", MMPTR(0xe0000834+4*i));
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for(i=0;i<8;i++)
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printf("%08x ", MMPTR(0xe0000884+4*i));
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printf("\n");
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}
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void ddrwr(char *startaddr)
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{
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char *c;
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unsigned int addr;
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int i;
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if(*startaddr == 0) {
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printf("ddrrd <address>\n");
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return;
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}
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addr = strtoul(startaddr, &c, 0);
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if(*c != 0) {
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printf("incorrect address\n");
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return;
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}
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for(i=0;i<8;i++) {
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MMPTR(0xe0000814+4*i) = i;
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MMPTR(0xe0000864+4*i) = i;
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}
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setaddr(addr);
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CSR_DFII_BA_P1 = 0;
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CSR_DFII_COMMAND_P1 = DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS|DFII_COMMAND_WRDATA;
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}
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int ddrinit(void)
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{
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printf("Initializing DDR SDRAM...\n");
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init_sequence();
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setaddr(0x0000);
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CSR_DFII_BA_P0 = 0;
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CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_CS;
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cdelay(15);
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return 1;
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}
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@ -19,5 +19,7 @@
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#define __DDRINIT_H
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int ddrinit(void);
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void ddrrd(char *startaddr);
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void ddrwr(char *startaddr);
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#endif /* __DDRINIT_H */
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@ -353,6 +353,8 @@ static void do_command(char *c)
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else if(strcmp(token, "wcsr") == 0) wcsr(get_token(&c), get_token(&c));
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else if(strcmp(token, "ddrinit") == 0) ddrinit();
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else if(strcmp(token, "ddrrd") == 0) ddrrd(get_token(&c));
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else if(strcmp(token, "ddrwr") == 0) ddrwr(get_token(&c));
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else if(strcmp(token, "") != 0)
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printf("Command not found\n");
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@ -25,22 +25,53 @@
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#define DFII_CONTROL_SEL (0x01)
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#define DFII_CONTROL_CKE (0x02)
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#define CSR_DFII_COMMAND MMPTR(0xe0001004)
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#define CSR_DFII_COMMAND_P0 MMPTR(0xe0000804)
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#define CSR_DFII_AH_P0 MMPTR(0xe0000808)
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#define CSR_DFII_AL_P0 MMPTR(0xe000080C)
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#define CSR_DFII_BA_P0 MMPTR(0xe0000810)
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#define CSR_DFII_WD0_P0 MMPTR(0xe0000814)
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#define CSR_DFII_WD1_P0 MMPTR(0xe0000818)
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#define CSR_DFII_WD2_P0 MMPTR(0xe000081C)
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#define CSR_DFII_WD3_P0 MMPTR(0xe0000820)
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#define CSR_DFII_WD4_P0 MMPTR(0xe0000824)
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#define CSR_DFII_WD5_P0 MMPTR(0xe0000828)
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#define CSR_DFII_WD6_P0 MMPTR(0xe000082C)
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#define CSR_DFII_WD7_P0 MMPTR(0xe0000830)
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#define CSR_DFII_RD0_P0 MMPTR(0xe0000834)
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#define CSR_DFII_RD1_P0 MMPTR(0xe0000838)
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#define CSR_DFII_RD2_P0 MMPTR(0xe000083C)
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#define CSR_DFII_RD3_P0 MMPTR(0xe0000840)
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#define CSR_DFII_RD4_P0 MMPTR(0xe0000844)
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#define CSR_DFII_RD5_P0 MMPTR(0xe0000848)
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#define CSR_DFII_RD6_P0 MMPTR(0xe000084C)
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#define CSR_DFII_RD7_P0 MMPTR(0xe0000850)
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#define CSR_DFII_COMMAND_P1 MMPTR(0xe0000854)
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#define CSR_DFII_AH_P1 MMPTR(0xe0000858)
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#define CSR_DFII_AL_P1 MMPTR(0xe000085C)
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#define CSR_DFII_BA_P1 MMPTR(0xe0000860)
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#define CSR_DFII_WD0_P1 MMPTR(0xe0000864)
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#define CSR_DFII_WD1_P1 MMPTR(0xe0000868)
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#define CSR_DFII_WD2_P1 MMPTR(0xe000086C)
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#define CSR_DFII_WD3_P1 MMPTR(0xe0000870)
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#define CSR_DFII_WD4_P1 MMPTR(0xe0000874)
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#define CSR_DFII_WD5_P1 MMPTR(0xe0000878)
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#define CSR_DFII_WD6_P1 MMPTR(0xe000087C)
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#define CSR_DFII_WD7_P1 MMPTR(0xe0000880)
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#define CSR_DFII_RD0_P1 MMPTR(0xe0000884)
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#define CSR_DFII_RD1_P1 MMPTR(0xe0000888)
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#define CSR_DFII_RD2_P1 MMPTR(0xe000088C)
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#define CSR_DFII_RD3_P1 MMPTR(0xe0000890)
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#define CSR_DFII_RD4_P1 MMPTR(0xe0000894)
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#define CSR_DFII_RD5_P1 MMPTR(0xe0000898)
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#define CSR_DFII_RD6_P1 MMPTR(0xe000089C)
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#define CSR_DFII_RD7_P1 MMPTR(0xe00008a0)
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#define DFII_COMMAND_CS (0x01)
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#define DFII_COMMAND_WE (0x02)
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#define DFII_COMMAND_CAS (0x04)
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#define DFII_COMMAND_RAS (0x08)
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#define DFII_COMMAND_RDDATA (0x10)
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#define DFII_COMMAND_WRDATA (0x20)
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#define CSR_DFII_AH MMPTR(0xe0000808)
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#define CSR_DFII_AL MMPTR(0xe000080C)
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#define CSR_DFII_BA MMPTR(0xe0000810)
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#define CSR_DFII_RDDELAY MMPTR(0xe0000814)
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#define CSR_DFII_RDDURATION MMPTR(0xe0000818)
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#define CSR_DFII_WRDELAY MMPTR(0xe000081C)
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#define CSR_DFII_WRDURATION MMPTR(0xe0000820)
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#define DFII_COMMAND_WRDATA (0x10)
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#define DFII_COMMAND_RDDATA (0x20)
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#endif /* __HW_DFII_H */
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