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sim: default runner to Icarus Verilog

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This commit is contained in:
Sebastien Bourdeauducq 2013-02-09 17:04:53 +01:00
parent bd6856ba7a
commit 92b67df41c
13 changed files with 23 additions and 32 deletions
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2
doc/simulation.rst
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@ -36,8 +36,8 @@ Creating a simulator object
The constructor of the ``Simulator`` object takes the following parameters: The constructor of the ``Simulator`` object takes the following parameters:
#. The fragment to simulate. The fragment can (and generally does) contain both synthesizable code and a non-synthesizable list of simulation functions. #. The fragment to simulate. The fragment can (and generally does) contain both synthesizable code and a non-synthesizable list of simulation functions.
#. A simulator runner object (see :ref:`simrunner`).
#. A top-level object (see :ref:`toplevel`). With the default value of ``None``, the simulator creates a default top-level object itself. #. A top-level object (see :ref:`toplevel`). With the default value of ``None``, the simulator creates a default top-level object itself.
#. A simulator runner object (see :ref:`simrunner`). With the default value of ``None``, Icarus Verilog is used with the default parameters.
#. The name of the UNIX domain socket used to communicate with the external simulator through the VPI plug-in (default: "simsocket"). #. The name of the UNIX domain socket used to communicate with the external simulator through the VPI plug-in (default: "simsocket").
#. Additional keyword arguments (if any) are passed to the Verilog conversion function. #. Additional keyword arguments (if any) are passed to the Verilog conversion function.

5
examples/dataflow/dma.py
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@ -6,7 +6,6 @@ from migen.actorlib import dma_wishbone, dma_asmi
from migen.actorlib.sim import * from migen.actorlib.sim import *
from migen.bus import wishbone, asmibus from migen.bus import wishbone, asmibus
from migen.sim.generic import Simulator from migen.sim.generic import Simulator
from migen.sim.icarus import Runner
class MyModel: class MyModel:
def read(self, address): def read(self, address):
@ -51,7 +50,7 @@ def wishbone_sim(efragment, master, end_simulation):
+ tap.get_fragment() \ + tap.get_fragment() \
+ interconnect.get_fragment() \ + interconnect.get_fragment() \
+ Fragment(sim=[_end_simulation]) + Fragment(sim=[_end_simulation])
sim = Simulator(fragment, Runner()) sim = Simulator(fragment)
sim.run() sim.run()
def asmi_sim(efragment, hub, end_simulation): def asmi_sim(efragment, hub, end_simulation):
@ -65,7 +64,7 @@ def asmi_sim(efragment, hub, end_simulation):
+ peripheral.get_fragment() \ + peripheral.get_fragment() \
+ tap.get_fragment() \ + tap.get_fragment() \
+ Fragment(sim=[_end_simulation]) + Fragment(sim=[_end_simulation])
sim = Simulator(fragment, Runner()) sim = Simulator(fragment)
sim.run() sim.run()
def test_wb_reader(): def test_wb_reader():

3
examples/dataflow/misc.py
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@ -3,7 +3,6 @@ from migen.flow.transactions import *
from migen.actorlib import misc from migen.actorlib import misc
from migen.actorlib.sim import * from migen.actorlib.sim import *
from migen.sim.generic import Simulator from migen.sim.generic import Simulator
from migen.sim.icarus import Runner
def source_gen(): def source_gen():
for i in range(10): for i in range(10):
@ -26,7 +25,7 @@ def main():
g.add_connection(loop, sink) g.add_connection(loop, sink)
comp = CompositeActor(g) comp = CompositeActor(g)
fragment = comp.get_fragment() fragment = comp.get_fragment()
sim = Simulator(fragment, Runner()) sim = Simulator(fragment)
sim.run(500) sim.run(500)
main() main()

3
examples/dataflow/structuring.py
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@ -8,7 +8,6 @@ from migen.flow.transactions import *
from migen.actorlib import structuring from migen.actorlib import structuring
from migen.actorlib.sim import * from migen.actorlib.sim import *
from migen.sim.generic import Simulator from migen.sim.generic import Simulator
from migen.sim.icarus import Runner
from migen.flow import perftools from migen.flow import perftools
pack_factor = 5 pack_factor = 5
@ -47,7 +46,7 @@ def main():
reporter = perftools.DFGReporter(g) reporter = perftools.DFGReporter(g)
fragment = comp.get_fragment() + reporter.get_fragment() fragment = comp.get_fragment() + reporter.get_fragment()
sim = Simulator(fragment, Runner()) sim = Simulator(fragment)
sim.run(1000) sim.run(1000)
g_layout = nx.spectral_layout(g) g_layout = nx.spectral_layout(g)

3
examples/pytholite/basic.py
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@ -3,7 +3,6 @@ from migen.flow.transactions import *
from migen.actorlib.sim import * from migen.actorlib.sim import *
from migen.pytholite.compiler import make_pytholite from migen.pytholite.compiler import make_pytholite
from migen.sim.generic import Simulator from migen.sim.generic import Simulator
from migen.sim.icarus import Runner
from migen.fhdl import verilog from migen.fhdl import verilog
layout = [("r", 32)] layout = [("r", 32)]
@ -19,7 +18,7 @@ def run_sim(ng):
c = CompositeActor(g) c = CompositeActor(g)
fragment = c.get_fragment() fragment = c.get_fragment()
sim = Simulator(fragment, Runner()) sim = Simulator(fragment)
sim.run(30) sim.run(30)
del sim del sim

3
examples/pytholite/uio.py
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@ -7,7 +7,6 @@ from migen.uio.ioo import UnifiedIOSimulation
from migen.pytholite.transel import Register from migen.pytholite.transel import Register
from migen.pytholite.compiler import make_pytholite from migen.pytholite.compiler import make_pytholite
from migen.sim.generic import Simulator from migen.sim.generic import Simulator
from migen.sim.icarus import Runner
from migen.fhdl import verilog from migen.fhdl import verilog
layout = [("r", 32)] layout = [("r", 32)]
@ -40,7 +39,7 @@ def run_sim(ng):
c = CompositeActor(g) c = CompositeActor(g)
fragment = slave.get_fragment() + intercon.get_fragment() + c.get_fragment() fragment = slave.get_fragment() + intercon.get_fragment() + c.get_fragment()
sim = Simulator(fragment, Runner()) sim = Simulator(fragment)
sim.run(50) sim.run(50)
del sim del sim

5
examples/sim/abstract_transactions.py
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@ -8,7 +8,6 @@ from migen.fhdl import autofragment
from migen.bus.transactions import * from migen.bus.transactions import *
from migen.bus import wishbone, asmibus from migen.bus import wishbone, asmibus
from migen.sim.generic import Simulator from migen.sim.generic import Simulator
from migen.sim.icarus import Runner
# Our bus master. # Our bus master.
# Python generators let us program bus transactions in an elegant sequential style. # Python generators let us program bus transactions in an elegant sequential style.
@ -67,7 +66,7 @@ def test_wishbone():
def end_simulation(s): def end_simulation(s):
s.interrupt = master.done s.interrupt = master.done
fragment = autofragment.from_local() + Fragment(sim=[end_simulation]) fragment = autofragment.from_local() + Fragment(sim=[end_simulation])
sim = Simulator(fragment, Runner()) sim = Simulator(fragment)
sim.run() sim.run()
def test_asmi(): def test_asmi():
@ -85,7 +84,7 @@ def test_asmi():
def end_simulation(s): def end_simulation(s):
s.interrupt = master.done s.interrupt = master.done
fragment = autofragment.from_local() + Fragment(sim=[end_simulation]) fragment = autofragment.from_local() + Fragment(sim=[end_simulation])
sim = Simulator(fragment, Runner()) sim = Simulator(fragment)
sim.run() sim.run()
test_wishbone() test_wishbone()

6
examples/sim/basic1.py
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@ -3,7 +3,6 @@
from migen.fhdl.structure import * from migen.fhdl.structure import *
from migen.sim.generic import Simulator from migen.sim.generic import Simulator
from migen.sim.icarus import Runner
# Our simple counter, which increments at every cycle # Our simple counter, which increments at every cycle
# and prints its current value in simulation. # and prints its current value in simulation.
@ -31,9 +30,8 @@ class Counter:
def main(): def main():
dut = Counter() dut = Counter()
# Use the Icarus Verilog runner. # We do not specify a top-level nor runner object, and use the defaults.
# We do not specify a top-level object, and use the default. sim = Simulator(dut.get_fragment())
sim = Simulator(dut.get_fragment(), Runner())
# Since we do not use sim.interrupt, limit the simulation # Since we do not use sim.interrupt, limit the simulation
# to some number of cycles. # to some number of cycles.
sim.run(20) sim.run(20)

3
examples/sim/basic2.py
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@ -3,7 +3,6 @@
from migen.fhdl.structure import * from migen.fhdl.structure import *
from migen.sim.generic import Simulator, TopLevel from migen.sim.generic import Simulator, TopLevel
from migen.sim.icarus import Runner
# A slightly improved counter. # A slightly improved counter.
# Has a clock enable (CE) signal, counts on more bits # Has a clock enable (CE) signal, counts on more bits
@ -46,7 +45,7 @@ def main():
dut = Counter() dut = Counter()
# Instantiating the generic top-level ourselves lets us # Instantiating the generic top-level ourselves lets us
# specify a VCD output file. # specify a VCD output file.
sim = Simulator(dut.get_fragment(), Runner(), TopLevel("my.vcd")) sim = Simulator(dut.get_fragment(), TopLevel("my.vcd"))
sim.run(20) sim.run(20)
main() main()

3
examples/sim/dataflow.py
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@ -4,7 +4,6 @@ from migen.flow.transactions import *
from migen.flow.network import * from migen.flow.network import *
from migen.actorlib.sim import * from migen.actorlib.sim import *
from migen.sim.generic import Simulator from migen.sim.generic import Simulator
from migen.sim.icarus import Runner
def source_gen(): def source_gen():
for i in range(10): for i in range(10):
@ -26,7 +25,7 @@ def main():
def end_simulation(s): def end_simulation(s):
s.interrupt = source.token_exchanger.done s.interrupt = source.token_exchanger.done
fragment = comp.get_fragment() + Fragment(sim=[end_simulation]) fragment = comp.get_fragment() + Fragment(sim=[end_simulation])
sim = Simulator(fragment, Runner()) sim = Simulator(fragment)
sim.run() sim.run()
main() main()

3
examples/sim/fir.py
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@ -10,7 +10,6 @@ from migen.fhdl import verilog
from migen.corelogic.misc import optree from migen.corelogic.misc import optree
from migen.fhdl import autofragment from migen.fhdl import autofragment
from migen.sim.generic import Simulator, PureSimulable from migen.sim.generic import Simulator, PureSimulable
from migen.sim.icarus import Runner
# A synthesizable FIR filter. # A synthesizable FIR filter.
class FIR: class FIR:
@ -63,7 +62,7 @@ def main():
for frequency in [0.05, 0.07, 0.1, 0.15, 0.2]: for frequency in [0.05, 0.07, 0.1, 0.15, 0.2]:
tb = TB(fir, frequency) tb = TB(fir, frequency)
fragment = autofragment.from_local() fragment = autofragment.from_local()
sim = Simulator(fragment, Runner()) sim = Simulator(fragment)
sim.run(100) sim.run(100)
del sim del sim
in_signals += tb.inputs in_signals += tb.inputs

3
examples/sim/memory.py
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@ -3,7 +3,6 @@
from migen.fhdl.structure import * from migen.fhdl.structure import *
from migen.sim.generic import Simulator from migen.sim.generic import Simulator
from migen.sim.icarus import Runner
class Mem: class Mem:
def __init__(self): def __init__(self):
@ -29,7 +28,7 @@ class Mem:
def main(): def main():
dut = Mem() dut = Mem()
sim = Simulator(dut.get_fragment(), Runner()) sim = Simulator(dut.get_fragment())
# No need for a cycle limit here, we use sim.interrupt instead. # No need for a cycle limit here, we use sim.interrupt instead.
sim.run() sim.run()

13
migen/sim/generic.py
View file

@ -4,6 +4,7 @@
from migen.fhdl.structure import * from migen.fhdl.structure import *
from migen.fhdl import verilog from migen.fhdl import verilog
from migen.sim.ipc import * from migen.sim.ipc import *
from migen.sim import icarus
class TopLevel: class TopLevel:
def __init__(self, vcd_name=None, vcd_level=1, def __init__(self, vcd_name=None, vcd_level=1,
@ -73,13 +74,15 @@ end
return r return r
class Simulator: class Simulator:
def __init__(self, fragment, sim_runner, top_level=None, sockaddr="simsocket", **vopts): def __init__(self, fragment, top_level=None, sim_runner=None, sockaddr="simsocket", **vopts):
self.fragment = fragment
if top_level is None: if top_level is None:
self.top_level = TopLevel() top_level = TopLevel()
else: if sim_runner is None:
self.top_level = top_level sim_runner = icarus.Runner()
self.fragment = fragment
self.top_level = top_level
self.ipc = Initiator(sockaddr) self.ipc = Initiator(sockaddr)
self.sim_runner = sim_runner
c_top = self.top_level.get(sockaddr) c_top = self.top_level.get(sockaddr)