Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity

cpu/vexriscv: bump submodule

Browse source
This commit is contained in:
Mateusz Holenko 2019-07-25 08:43:35 +02:00
parent bc7ab637dd
commit 932475a29b
1 changed files with 1 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
litex/soc/cores/cpu/vexriscv/verilog

@ -1 +1 @@
Subproject commit 747a2e012f43d13c3487acc3c758477aad277559 Subproject commit 854f9bd2282c97251ce65e4117c5cf1630722004