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cpu/rocket: add "octo" (512 bit wide) "full" variants 

Boards such as the Xilinx VC707, STLV7325, etc. offer support for
dual-rank memory, which results in a 512-bit wide native LiteDRAM
port. These additional "8x wide" (or "octo") variants support that
width directly, without the need for additional data width conversion
that whould have to be implemented on the LiteX side of the SoC.

Suggested-by: Icenowy Zheng <uwu@icenowy.me>
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
This commit is contained in:
Gabriel Somlo 2022-12-03 18:09:44 -05:00
parent 85f762cd1c
commit 937428b1fc
1 changed files with 9 additions and 0 deletions
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9
litex/soc/cores/cpu/rocket/core.py
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@ -55,6 +55,9 @@ CPU_VARIANTS = {
"full4d": "freechips.rocketchip.system.LitexFull4DConfig",
"fullq": "freechips.rocketchip.system.LitexFullQConfig",
"full4q": "freechips.rocketchip.system.LitexFull4QConfig",
"fullo": "freechips.rocketchip.system.LitexFullOConfig",
"full4o": "freechips.rocketchip.system.LitexFull4OConfig",
"full8o": "freechips.rocketchip.system.LitexFull8OConfig",
}
# GCC Flags-----------------------------------------------------------------------------------------
@ -72,6 +75,9 @@ GCC_FLAGS = {
"full4d": "-march=rv64imafdc -mabi=lp64 ",
"fullq": "-march=rv64imafdc -mabi=lp64 ",
"full4q": "-march=rv64imafdc -mabi=lp64 ",
"fullo": "-march=rv64imafdc -mabi=lp64 ",
"full4o": "-march=rv64imafdc -mabi=lp64 ",
"full8o": "-march=rv64imafdc -mabi=lp64 ",
}
# CPU Size Params ----------------------------------------------------------------------------------
@ -90,6 +96,9 @@ CPU_SIZE_PARAMS = {
"full4d": ( 128, 64, 4),
"fullq": ( 256, 64, 1),
"full4q": ( 256, 64, 4),
"fullo": ( 512, 64, 1),
"full4o": ( 512, 64, 4),
"full8o": ( 512, 64, 8),
}
# Rocket ------------------------------------------------------------------------------------------