soc/interconnect/axi: implement AXILite down-converter
This commit is contained in:
Jędrzej Boczar
parent
0be607dad9
commit
93bcc94b53
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@ -172,13 +172,14 @@ class AXILiteInterface:
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yield
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while not (yield self.aw.ready):
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yield
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yield self.aw.valid.eq(0)
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while not (yield self.w.ready):
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yield
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yield self.w.valid.eq(0)
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yield self.b.ready.eq(1)
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while not (yield self.b.valid):
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yield
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yield self.b.ready.eq(1)
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resp = (yield self.b.resp)
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yield
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yield self.b.ready.eq(0)
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return resp
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@ -188,12 +189,12 @@ class AXILiteInterface:
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yield
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while not (yield self.ar.ready):
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yield
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yield self.ar.valid.eq(0)
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yield self.r.ready.eq(1)
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while not (yield self.r.valid):
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yield
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yield self.r.ready.eq(1)
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data = (yield self.r.data)
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resp = (yield self.r.resp)
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yield
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yield self.r.ready.eq(0)
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return (data, resp)
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@ -679,6 +680,152 @@ class AXILiteSRAM(Module):
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# AXILite Data Width Converter ---------------------------------------------------------------------
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class AXILiteDownConverter(Module):
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def __init__(self, master, slave):
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assert isinstance(master, AXILiteInterface) and isinstance(slave, AXILiteInterface)
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dw_from = len(master.r.data)
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dw_to = len(slave.r.data)
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ratio = dw_from//dw_to
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# # #
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skip = Signal()
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counter = Signal(max=ratio)
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do_read = Signal()
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do_write = Signal()
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last_was_read = Signal()
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aw_ready = Signal()
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w_ready = Signal()
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# Slave address counter
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master_align = log2_int(master.data_width//8)
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slave_align = log2_int(slave.data_width//8)
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addr_counter = Signal(master_align)
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self.comb += addr_counter[slave_align:].eq(counter)
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# Write path
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self.comb += [
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slave.aw.addr.eq(Cat(addr_counter, master.aw.addr[master_align:])),
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Case(counter, {i: slave.w.data.eq(master.w.data[i*dw_to:]) for i in range(ratio)}),
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Case(counter, {i: slave.w.strb.eq(master.w.strb[i*dw_to//8:]) for i in range(ratio)}),
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master.b.resp.eq(RESP_OKAY), # FIXME: error handling?
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]
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# Read path
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# shift the data word
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r_data = Signal(dw_from, reset_less=True)
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self.sync += If(slave.r.ready, r_data.eq(master.r.data))
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self.comb += master.r.data.eq(Cat(r_data[dw_to:], slave.r.data))
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# address, resp
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self.comb += [
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slave.ar.addr.eq(Cat(addr_counter, master.ar.addr[master_align:])),
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master.r.resp.eq(RESP_OKAY), # FIXME: error handling?
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]
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# Control Path
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fsm = FSM(reset_state="IDLE")
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fsm = ResetInserter()(fsm)
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self.submodules.fsm = fsm
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self.comb += fsm.reset.eq(~(master.aw.valid | master.ar.valid))
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fsm.act("IDLE",
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NextValue(counter, 0),
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# If the last access was a read, do a write, and vice versa
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If(master.aw.valid & master.ar.valid,
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do_write.eq(last_was_read),
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do_read.eq(~last_was_read),
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).Else(
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do_write.eq(master.aw.valid),
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do_read.eq(master.ar.valid),
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),
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# Start reading/writing immediately not to waste a cycle
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If(do_write & master.w.valid,
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NextValue(last_was_read, 0),
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NextState("WRITE")
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).Elif(do_read,
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NextValue(last_was_read, 1),
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NextState("READ")
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)
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)
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# Write conversion
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fsm.act("WRITE",
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skip.eq(slave.w.strb == 0),
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slave.aw.valid.eq(~skip & ~aw_ready),
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slave.w.valid.eq(~skip & ~w_ready),
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If(slave.aw.ready,
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NextValue(aw_ready, 1)
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),
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If(slave.w.ready,
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NextValue(w_ready, 1)
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),
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# When skipping, we just increment the counter
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If(skip,
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NextValue(counter, counter + 1),
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# Corner-case: when the last word is being skipped, we must send the response
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If(counter == (ratio - 1),
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master.aw.ready.eq(1),
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master.w.ready.eq(1),
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NextState("WRITE-RESPONSE-MASTER")
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)
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# Write current word and wait for write response
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).Elif((slave.aw.ready | aw_ready) & (slave.w.ready | w_ready),
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NextState("WRITE-RESPONSE-SLAVE")
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)
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)
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fsm.act("WRITE-RESPONSE-SLAVE",
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NextValue(aw_ready, 0),
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NextValue(w_ready, 0),
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If(slave.b.valid,
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slave.b.ready.eq(1),
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If(counter == (ratio - 1),
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master.aw.ready.eq(1),
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master.w.ready.eq(1),
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NextState("WRITE-RESPONSE-MASTER")
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).Else(
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NextValue(counter, counter + 1),
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NextState("WRITE")
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)
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)
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)
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fsm.act("WRITE-RESPONSE-MASTER",
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NextValue(aw_ready, 0),
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NextValue(w_ready, 0),
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master.b.valid.eq(1),
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If(master.b.ready,
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NextState("IDLE")
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)
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)
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# Read conversion
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fsm.act("READ",
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slave.ar.valid.eq(1),
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If(slave.ar.ready,
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NextState("READ-RESPONSE-SLAVE")
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)
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)
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fsm.act("READ-RESPONSE-SLAVE",
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If(slave.r.valid,
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# On last word acknowledge ar and hold slave.r.valid until we get master.r.ready
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If(counter == (ratio - 1),
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master.ar.ready.eq(1),
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NextState("READ-RESPONSE-MASTER")
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# Acknowledge the response and continue conversion
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).Else(
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slave.r.ready.eq(1),
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NextValue(counter, counter + 1),
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NextState("READ")
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)
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)
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)
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fsm.act("READ-RESPONSE-MASTER",
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master.r.valid.eq(1),
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If(master.r.ready,
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slave.r.ready.eq(1),
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NextState("IDLE")
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)
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)
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class AXILiteConverter(Module):
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"""AXILite data width converter"""
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def __init__(self, master, slave):
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@ -690,8 +837,10 @@ class AXILiteConverter(Module):
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dw_from = len(master.r.data)
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dw_to = len(slave.r.data)
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if dw_from > dw_to:
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raise NotImplementedError
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print("AXILiteConverter (Down): {} -> {}".format(master.data_width, slave.data_width))
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self.submodules += AXILiteDownConverter(master, slave)
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elif dw_from < dw_to:
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print("AXILiteConverter (Up): {} -> {}".format(master.data_width, slave.data_width))
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raise NotImplementedError
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else:
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self.comb += master.connect(slave)
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200
test/test_axi.py
200
test/test_axi.py
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@ -51,7 +51,7 @@ class Write(Access):
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class Read(Access):
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pass
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# Tests --------------------------------------------------------------------------------------------
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# TestAXI ------------------------------------------------------------------------------------------
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class TestAXI(unittest.TestCase):
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def test_burst2beat(self):
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@ -327,6 +327,71 @@ class TestAXI(unittest.TestCase):
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r_ready_random = 90
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)
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# TestAXILite --------------------------------------------------------------------------------------
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class AXILiteChecker:
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def __init__(self, latency=None, rdata_generator=None):
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self.latency = latency or (lambda: 0)
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self.rdata_generator = rdata_generator or (lambda adr: 0xbaadc0de)
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self.writes = []
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self.reads = []
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def delay(self):
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for _ in range(self.latency()):
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yield
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def handle_write(self, axi_lite):
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while not (yield axi_lite.aw.valid):
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yield
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yield from self.delay()
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addr = (yield axi_lite.aw.addr)
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yield axi_lite.aw.ready.eq(1)
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yield
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yield axi_lite.aw.ready.eq(0)
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while not (yield axi_lite.w.valid):
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yield
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yield from self.delay()
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data = (yield axi_lite.w.data)
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strb = (yield axi_lite.w.strb)
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yield axi_lite.w.ready.eq(1)
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yield
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yield axi_lite.w.ready.eq(0)
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yield axi_lite.b.valid.eq(1)
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yield axi_lite.b.resp.eq(RESP_OKAY)
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yield
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while not (yield axi_lite.b.ready):
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yield
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yield axi_lite.b.valid.eq(0)
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self.writes.append((addr, data, strb))
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def handle_read(self, axi_lite):
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while not (yield axi_lite.ar.valid):
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yield
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yield from self.delay()
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addr = (yield axi_lite.ar.addr)
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yield axi_lite.ar.ready.eq(1)
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yield
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yield axi_lite.ar.ready.eq(0)
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data = self.rdata_generator(addr)
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yield axi_lite.r.valid.eq(1)
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yield axi_lite.r.resp.eq(RESP_OKAY)
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yield axi_lite.r.data.eq(data)
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yield
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while not (yield axi_lite.r.ready):
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yield
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yield axi_lite.r.valid.eq(0)
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self.reads.append((addr, data))
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@passive
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def handler(self, axi_lite):
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while True:
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if (yield axi_lite.aw.valid):
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yield from self.handle_write(axi_lite)
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if (yield axi_lite.ar.valid):
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yield from self.handle_read(axi_lite)
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yield
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class TestAXILite(unittest.TestCase):
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def test_wishbone2axi2wishbone(self):
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class DUT(Module):
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def __init__(self):
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@ -439,3 +504,136 @@ class TestAXI(unittest.TestCase):
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dut = DUT(size=len(init)*4, init=[v for v in init])
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run_simulation(dut, [generator(dut, init)])
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self.assertEqual(dut.errors, 0)
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def converter_test(self, width_from, width_to,
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write_pattern=None, write_expected=None,
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read_pattern=None, read_expected=None):
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assert not (write_pattern is None and read_pattern is None)
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if write_pattern is None:
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write_pattern = []
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write_expected = []
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elif len(write_pattern[0]) == 2:
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# add w.strb
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write_pattern = [(adr, data, 2**(width_from//8)-1) for adr, data in write_pattern]
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if read_pattern is None:
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read_pattern = []
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read_expected = []
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class DUT(Module):
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def __init__(self, width_from, width_to):
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self.master = AXILiteInterface(data_width=width_from)
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self.slave = AXILiteInterface(data_width=width_to)
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self.submodules.converter = AXILiteConverter(self.master, self.slave)
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def generator(axi_lite):
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for addr, data, strb in write_pattern or []:
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resp = (yield from axi_lite.write(addr, data, strb))
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self.assertEqual(resp, RESP_OKAY)
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for _ in range(16):
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yield
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for addr, refdata in read_pattern or []:
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data, resp = (yield from axi_lite.read(addr))
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self.assertEqual(resp, RESP_OKAY)
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self.assertEqual(data, refdata)
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for _ in range(4):
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yield
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def rdata_generator(adr):
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for a, v in read_expected:
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if a == adr:
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return v
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return 0xbaadc0de
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_latency = 0
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def latency():
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nonlocal _latency
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_latency = (_latency + 1) % 3
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return _latency
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dut = DUT(width_from=width_from, width_to=width_to)
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checker = AXILiteChecker(latency, rdata_generator)
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run_simulation(dut, [generator(dut.master), checker.handler(dut.slave)], vcd_name='sim.vcd')
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self.assertEqual(checker.writes, write_expected)
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self.assertEqual(checker.reads, read_expected)
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def test_axilite_down_converter_32to16(self):
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write_pattern = [
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(0x00000000, 0x22221111),
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(0x00000004, 0x44443333),
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(0x00000008, 0x66665555),
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(0x00000100, 0x88887777),
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]
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write_expected = [
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(0x00000000, 0x1111, 0b11),
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(0x00000002, 0x2222, 0b11),
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(0x00000004, 0x3333, 0b11),
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(0x00000006, 0x4444, 0b11),
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(0x00000008, 0x5555, 0b11),
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(0x0000000a, 0x6666, 0b11),
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(0x00000100, 0x7777, 0b11),
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(0x00000102, 0x8888, 0b11),
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]
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read_pattern = write_pattern
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read_expected = [(adr, data) for (adr, data, _) in write_expected]
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self.converter_test(width_from=32, width_to=16,
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write_pattern=write_pattern, write_expected=write_expected,
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read_pattern=read_pattern, read_expected=read_expected)
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def test_axilite_down_converter_32to8(self):
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write_pattern = [
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(0x00000000, 0x44332211),
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(0x00000004, 0x88776655),
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]
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write_expected = [
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(0x00000000, 0x11, 0b1),
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(0x00000001, 0x22, 0b1),
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(0x00000002, 0x33, 0b1),
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(0x00000003, 0x44, 0b1),
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(0x00000004, 0x55, 0b1),
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(0x00000005, 0x66, 0b1),
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(0x00000006, 0x77, 0b1),
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(0x00000007, 0x88, 0b1),
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]
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read_pattern = write_pattern
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read_expected = [(adr, data) for (adr, data, _) in write_expected]
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self.converter_test(width_from=32, width_to=8,
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write_pattern=write_pattern, write_expected=write_expected,
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read_pattern=read_pattern, read_expected=read_expected)
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def test_axilite_down_converter_64to32(self):
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write_pattern = [
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(0x00000000, 0x2222222211111111),
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(0x00000008, 0x4444444433333333),
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]
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write_expected = [
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(0x00000000, 0x11111111, 0b1111),
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(0x00000004, 0x22222222, 0b1111),
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(0x00000008, 0x33333333, 0b1111),
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(0x0000000c, 0x44444444, 0b1111),
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]
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read_pattern = write_pattern
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read_expected = [(adr, data) for (adr, data, _) in write_expected]
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self.converter_test(width_from=64, width_to=32,
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write_pattern=write_pattern, write_expected=write_expected,
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read_pattern=read_pattern, read_expected=read_expected)
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def test_axilite_down_converter_strb(self):
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write_pattern = [
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(0x00000000, 0x22221111, 0b1100),
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(0x00000004, 0x44443333, 0b1111),
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(0x00000008, 0x66665555, 0b1011),
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(0x00000100, 0x88887777, 0b0011),
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]
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write_expected = [
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(0x00000002, 0x2222, 0b11),
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(0x00000004, 0x3333, 0b11),
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(0x00000006, 0x4444, 0b11),
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(0x00000008, 0x5555, 0b11),
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(0x0000000a, 0x6666, 0b10),
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(0x00000100, 0x7777, 0b11),
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]
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self.converter_test(width_from=32, width_to=16,
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write_pattern=write_pattern, write_expected=write_expected)
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