Efinix: add a local video.py with VideoLVDSPHY for testing
This commit is contained in:
Franck Jullien
parent
a08c5201ad
commit
93c470aecb
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#
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# This file is part of LiteX.
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#
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# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import math
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from migen import *
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from migen.genlib.cdc import MultiReg
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from litex.soc.interconnect.csr import *
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from litex.soc.interconnect import stream
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from litex.soc.cores.code_tmds import TMDSEncoder
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from litex.build.io import SDROutput, DDROutput
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# Video Constants ----------------------------------------------------------------------------------
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hbits = 12
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vbits = 12
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# Video Timings ------------------------------------------------------------------------------------
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video_timings = {
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"640x480@60Hz" : {
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"pix_clk" : 25.175e6,
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"h_active" : 640,
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"h_blanking" : 160,
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"h_sync_offset" : 16,
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"h_sync_width" : 96,
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"v_active" : 480,
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"v_blanking" : 45,
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"v_sync_offset" : 10,
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"v_sync_width" : 2,
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},
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"640x480@75Hz" : {
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"pix_clk" : 31.5e6,
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"h_active" : 640,
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"h_blanking" : 200,
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"h_sync_offset" : 16,
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"h_sync_width" : 64,
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"v_active" : 480,
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"v_blanking" : 20,
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"v_sync_offset" : 1,
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"v_sync_width" : 3,
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},
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"800x600@60Hz" : {
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"pix_clk" : 40e6,
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"h_active" : 800,
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"h_blanking" : 256,
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"h_sync_offset" : 40,
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"h_sync_width" : 128,
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"v_active" : 600,
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"v_blanking" : 28,
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"v_sync_offset" : 1,
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"v_sync_width" : 4,
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},
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"800x600@75Hz": {
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"pix_clk" : 49.5e6,
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"h_active" : 800,
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"h_blanking" : 256,
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"h_sync_offset" : 16,
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"h_sync_width" : 80,
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"v_active" : 600,
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"v_blanking" : 25,
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"v_sync_offset" : 1,
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"v_sync_width" : 3,
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},
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"1024x768@60Hz": {
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"pix_clk" : 65e6,
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"h_active" : 1024,
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"h_blanking" : 320,
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"h_sync_offset" : 24,
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"h_sync_width" : 136,
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"v_active" : 768,
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"v_blanking" : 38,
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"v_sync_offset" : 3,
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"v_sync_width" : 6,
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},
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"1024x768@75Hz": {
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"pix_clk" : 78.8e6,
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"h_active" : 1024,
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"h_blanking" : 288,
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"h_sync_offset" : 16,
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"h_sync_width" : 96,
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"v_active" : 768,
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"v_blanking" : 32,
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"v_sync_offset" : 1,
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"v_sync_width" : 3,
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},
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"1280x720@60Hz": {
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"pix_clk" : 74.25e6,
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"h_active" : 1280,
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"h_blanking" : 370,
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"h_sync_offset" : 220,
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"h_sync_width" : 40,
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"v_active" : 720,
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"v_blanking" : 30,
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"v_sync_offset" : 5,
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"v_sync_width" : 5,
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},
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"1920x1080@30Hz": {
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"pix_clk" : 89.01e6,
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"h_active" : 1920,
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"h_blanking" : 720,
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"h_sync_offset" : 528,
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"h_sync_width" : 44,
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"v_active" : 1080,
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"v_blanking" : 45,
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"v_sync_offset" : 4,
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"v_sync_width" : 5,
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},
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"1920x1080@60Hz": {
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"pix_clk" : 148.35e6,
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"h_active" : 1920,
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"h_blanking" : 280,
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"h_sync_offset" : 88,
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"h_sync_width" : 44,
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"v_active" : 1080,
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"v_blanking" : 45,
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"v_sync_offset" : 4,
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"v_sync_width" : 5,
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},
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"1920x1080@50Hz": {
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"pix_clk" : 148.5e6,
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"h_active" : 1920,
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"h_blanking" : 720,
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"h_sync_offset" : 528,
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"h_sync_width" : 44,
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"v_active" : 1080,
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"v_blanking" : 45,
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"v_sync_offset" : 4,
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"v_sync_width" : 5,
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},
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"1920x1200@60Hz": {
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"pix_clk" : 148.2e6,
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"h_active" : 1920,
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"h_blanking" : 80,
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"h_sync_offset" : 8,
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"h_sync_width" : 32,
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"v_active" : 1200,
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"v_blanking" : 35,
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"v_sync_offset" : 21,
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"v_sync_width" : 8,
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},
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}
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# Video Timing Generator ---------------------------------------------------------------------------
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video_timing_layout = [
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# Synchronization signals.
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("hsync", 1),
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("vsync", 1),
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("de", 1),
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# Extended/Optional synchronization signals.
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("hres", hbits),
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("vres", vbits),
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("hcount", hbits),
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("vcount", vbits),
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]
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video_data_layout = [
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# Synchronization signals.
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("hsync", 1),
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("vsync", 1),
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("de", 1),
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# Data signals.
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("r", 8),
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("g", 8),
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("b", 8),
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]
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video_data_layout_dual = [
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# Synchronization signals.
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("hsync", 2),
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("vsync", 2),
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("de", 2),
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# Data signals.
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("r", 16),
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("g", 16),
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("b", 16),
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]
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class VideoTimingGenerator(Module, AutoCSR):
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def __init__(self, default_video_timings="800x600@60Hz"):
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# Check / Get Video Timings (can be str or dict)
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if isinstance(default_video_timings, str):
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try:
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self.video_timings = vt = video_timings[default_video_timings]
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except KeyError:
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msg = [f"Video Timings {default_video_timings} not supported, availables:"]
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for video_timing in video_timings.keys():
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msg.append(f" - {video_timing} / {video_timings[video_timing]['pix_clk']/1e6:3.2f}MHz.")
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raise ValueError("\n".join(msg))
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else:
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self.video_timings = vt = default_video_timings
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# MMAP Control/Status Registers.
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self._enable = CSRStorage(reset=1)
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self._hres = CSRStorage(hbits, vt["h_active"])
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self._hsync_start = CSRStorage(hbits, vt["h_active"] + vt["h_sync_offset"])
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self._hsync_end = CSRStorage(hbits, vt["h_active"] + vt["h_sync_offset"] + vt["h_sync_width"])
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self._hscan = CSRStorage(hbits, vt["h_active"] + vt["h_blanking"])
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self._vres = CSRStorage(vbits, vt["v_active"])
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self._vsync_start = CSRStorage(vbits, vt["v_active"] + vt["v_sync_offset"])
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self._vsync_end = CSRStorage(vbits, vt["v_active"] + vt["v_sync_offset"] + vt["v_sync_width"])
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self._vscan = CSRStorage(vbits, vt["v_active"] + vt["v_blanking"])
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# Video Timing Source
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self.source = source = stream.Endpoint(video_timing_layout)
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# # #
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# Resynchronize Enable to Video clock domain.
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self.enable = enable = Signal()
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self.specials += MultiReg(self._enable.storage, enable)
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# Resynchronize Horizontal Timings to Video clock domain.
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self.hres = hres = Signal(hbits)
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self.hsync_start = hsync_start = Signal(hbits)
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self.hsync_end = hsync_end = Signal(hbits)
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self.hscan = hscan = Signal(hbits)
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self.specials += MultiReg(self._hres.storage, hres)
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self.specials += MultiReg(self._hsync_start.storage, hsync_start)
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self.specials += MultiReg(self._hsync_end.storage, hsync_end)
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self.specials += MultiReg(self._hscan.storage, hscan)
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# Resynchronize Vertical Timings to Video clock domain.
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self.vres = vres = Signal(vbits)
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self.vsync_start = vsync_start = Signal(vbits)
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self.vsync_end = vsync_end = Signal(vbits)
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self.vscan = vscan = Signal(vbits)
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self.specials += MultiReg(self._vres.storage, vres)
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self.specials += MultiReg(self._vsync_start.storage, vsync_start)
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self.specials += MultiReg(self._vsync_end.storage, vsync_end)
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self.specials += MultiReg(self._vscan.storage, vscan)
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# Generate timings.
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hactive = Signal()
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vactive = Signal()
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fsm = FSM(reset_state="IDLE")
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fsm = ResetInserter()(fsm)
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self.submodules.fsm = fsm
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self.comb += fsm.reset.eq(~enable)
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fsm.act("IDLE",
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NextValue(hactive, 0),
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NextValue(vactive, 0),
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NextValue(source.hres, hres),
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NextValue(source.vres, vres),
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NextValue(source.hcount, 0),
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NextValue(source.vcount, 0),
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NextState("RUN")
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)
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self.comb += source.de.eq(hactive & vactive) # DE when both HActive and VActive.
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self.sync += source.first.eq((source.hcount == 0) & (source.vcount == 0)),
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self.sync += source.last.eq( (source.hcount == hscan) & (source.vcount == vscan)),
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fsm.act("RUN",
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source.valid.eq(1),
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If(source.ready,
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# Increment HCount.
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NextValue(source.hcount, source.hcount + 1),
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# Generate HActive / HSync.
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If(source.hcount == 0, NextValue(hactive, 1)), # Start of HActive.
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If(source.hcount == hres, NextValue(hactive, 0)), # End of HActive.
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If(source.hcount == hsync_start, NextValue(source.hsync, 1)), # Start of HSync.
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If(source.hcount == hsync_end, NextValue(source.hsync, 0)), # End of HSync.
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# End of HScan.
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If(source.hcount == hscan,
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# Reset HCount.
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NextValue(source.hcount, 0),
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# Increment VCount.
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NextValue(source.vcount, source.vcount + 1),
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# Generate VActive / VSync.
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If(source.vcount == 0, NextValue(vactive, 1)), # Start of VActive.
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If(source.vcount == vres, NextValue(vactive, 0)), # End of HActive.
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If(source.vcount == vsync_start, NextValue(source.vsync, 1)), # Start of VSync.
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If(source.vcount == vsync_end, NextValue(source.vsync, 0)), # End of VSync.
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# End of VScan.
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If(source.vcount == vscan,
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# Reset VCount.
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NextValue(source.vcount, 0),
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)
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)
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)
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)
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# Video Patterns -----------------------------------------------------------------------------------
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class ColorBarsPattern(Module):
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"""Color Bars Pattern"""
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def __init__(self):
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self.enable = Signal(reset=1)
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self.vtg_sink = vtg_sink = stream.Endpoint(video_timing_layout)
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self.source = source = stream.Endpoint(video_data_layout)
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# # #
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enable = Signal()
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self.specials += MultiReg(self.enable, enable)
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# Control Path.
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pix = Signal(hbits)
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bar = Signal(3)
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fsm = FSM(reset_state="IDLE")
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fsm = ResetInserter()(fsm)
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self.submodules.fsm = fsm
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self.comb += fsm.reset.eq(~self.enable)
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fsm.act("IDLE",
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NextValue(pix, 0),
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NextValue(bar, 0),
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vtg_sink.ready.eq(1),
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If(vtg_sink.valid & vtg_sink.first & (vtg_sink.hcount == 0) & (vtg_sink.vcount == 0),
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vtg_sink.ready.eq(0),
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NextState("RUN")
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)
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)
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fsm.act("RUN",
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vtg_sink.connect(source, keep={"valid", "ready", "last", "de", "hsync", "vsync"}),
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If(source.valid & source.ready & source.de,
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NextValue(pix, pix + 1),
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If(pix == (vtg_sink.hres[3:] -1), # 8 Color Bars.
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NextValue(pix, 0),
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NextValue(bar, bar + 1)
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)
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)
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)
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# Data Path.
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color_bar = [
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# R G B
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[0xff, 0xff, 0xff], # White
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[0xff, 0xff, 0x00], # Yellow
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[0x00, 0xff, 0xff], # Cyan
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[0x00, 0xff, 0x00], # Green
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[0xff, 0x00, 0xff], # Purple
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[0xff, 0x00, 0x00], # Red
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[0x00, 0x00, 0xff], # Blue
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[0x00, 0x00, 0x00], # Black
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]
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cases = {}
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for i in range(8):
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cases[i] = [
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source.r.eq(color_bar[i][0]),
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source.g.eq(color_bar[i][1]),
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source.b.eq(color_bar[i][2])
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]
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self.comb += Case(bar, cases)
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class VideoLVDSPHY(Module):
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def __init__(self, platform, pads, pixel_clk='px_clk', px_clk_x3_5='px_clk_x3_5'):
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self.sink = sink = stream.Endpoint(video_data_layout_dual)
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# # #
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channel1 = Record(video_data_layout)
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channel2 = Record(video_data_layout)
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self.comb += [ channel1.r.eq(sink.r[0:8]),
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channel1.g.eq(sink.g[0:8]),
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channel1.b.eq(sink.b[0:8]),
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channel1.de.eq(sink.de[0]),
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channel1.vsync.eq(sink.vsync[0]),
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channel1.hsync.eq(sink.hsync[0]),
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channel2.r.eq(sink.r[7:16]),
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channel2.g.eq(sink.g[7:16]),
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channel2.b.eq(sink.b[7:16]),
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channel2.de.eq(sink.de[1]),
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channel2.vsync.eq(sink.vsync[1]),
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channel2.hsync.eq(sink.hsync[1]),
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]
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# Always ack Sink, no backpressure.
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self.comb += sink.ready.eq(1)
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# -------- LVDS CLOCK -----------
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name = platform.get_pin_name(pads.clk)
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pad = platform.get_pin_location(pads.clk)
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clk = platform.add_iface_io('hdmi_clk', 7)
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block = {'type':'LVDS',
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'mode':'OUTPUT',
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'name':name,
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'location':[pad[0]],
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'serialisation':7,
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'fast_clk':px_clk_x3_5,
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'slow_clk':pixel_clk,
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}
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platform.toolchain.ifacewriter.xml_blocks.append(block)
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platform.delete(pads.clk)
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# -------- LVDS DATA -----------
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lvds = []
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lvds.append((pads.rxpa1, platform.get_pin_name(pads.rxpa1), platform.get_pin_location(pads.rxpa1)))
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lvds.append((pads.rxpa2, platform.get_pin_name(pads.rxpa2), platform.get_pin_location(pads.rxpa2)))
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rxpa1 = platform.add_iface_io('hdmi_rxpa1', 7)
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rxpa2 = platform.add_iface_io('hdmi_rxpa2', 7)
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lvds.append((pads.rxpb1, platform.get_pin_name(pads.rxpb1), platform.get_pin_location(pads.rxpb1)))
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lvds.append((pads.rxpb2, platform.get_pin_name(pads.rxpb2), platform.get_pin_location(pads.rxpb2)))
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rxpb1 = platform.add_iface_io('hdmi_rxpb1', 7)
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rxpb2 = platform.add_iface_io('hdmi_rxpb2', 7)
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lvds.append((pads.rxpc1, platform.get_pin_name(pads.rxpc1), platform.get_pin_location(pads.rxpc1)))
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lvds.append((pads.rxpc2, platform.get_pin_name(pads.rxpc2), platform.get_pin_location(pads.rxpc2)))
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rxpc1 = platform.add_iface_io('hdmi_rxpc1', 7)
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rxpc2 = platform.add_iface_io('hdmi_rxpc2', 7)
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lvds.append((pads.rxpd1, platform.get_pin_name(pads.rxpd1), platform.get_pin_location(pads.rxpd1)))
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lvds.append((pads.rxpd2, platform.get_pin_name(pads.rxpd2), platform.get_pin_location(pads.rxpd2)))
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rxpd1 = platform.add_iface_io('hdmi_rxpd1', 7)
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rxpd2 = platform.add_iface_io('hdmi_rxpd2', 7)
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for signal, name, pad in lvds:
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block = {'type':'LVDS',
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'mode':'OUTPUT',
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'name':name,
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'location':[pad[0]],
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'serialisation':7,
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'fast_clk':px_clk_x3_5,
|
||||
'slow_clk':pixel_clk,
|
||||
|
||||
}
|
||||
platform.toolchain.ifacewriter.xml_blocks.append(block)
|
||||
platform.delete(signal)
|
||||
|
||||
self.comb += [ rxpa1.eq(Cat(channel1.g[2], channel1.r[7], channel1.r[6], channel1.r[5], channel1.r[4], channel1.r[3], channel1.r[2])),
|
||||
rxpb1.eq(Cat(channel1.b[3], channel1.b[2], channel1.g[7], channel1.g[6], channel1.g[5], channel1.g[4], channel1.g[3])),
|
||||
rxpc1.eq(Cat(channel1.de, channel1.vsync, channel1.hsync, channel1.b[7], channel1.b[6], channel1.b[5], channel1.b[4])),
|
||||
rxpd1.eq(Cat(0, channel1.b[7], channel1.b[7], channel1.g[7], channel1.g[7], channel1.r[7], channel1.r[7])),
|
||||
|
||||
rxpa2.eq(Cat(channel2.g[2], channel2.r[7], channel2.r[6], channel2.r[5], channel2.r[4], channel2.r[3], channel2.r[2])),
|
||||
rxpb2.eq(Cat(channel2.b[3], channel2.b[2], channel2.g[7], channel2.g[6], channel2.g[5], channel2.g[4], channel2.g[3])),
|
||||
rxpc2.eq(Cat(channel2.de, channel2.vsync, channel2.hsync, channel2.b[7], channel2.b[6], channel2.b[5], channel2.b[4])),
|
||||
rxpd2.eq(Cat(0, channel2.b[7], channel2.b[7], channel2.g[7], channel2.g[7], channel2.r[7], channel2.r[7])),
|
||||
|
||||
clk.eq(0b1100011),
|
||||
]
|
||||
Loading…
Reference in New Issue