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https://github.com/enjoy-digital/litex.git
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Merge pull request #122 from daveshah1/trellis_ulx3s
Switch Trellis build to use LPF constraints; working on ULX3S
This commit is contained in:
enjoy-digital
GitHub
commit
93c623251b
3 changed files with 47 additions and 99 deletions
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@ -36,6 +36,8 @@ _io = [
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Subsignal("dm", Pins("U19 E20")),
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IOStandard("LVCMOS33")
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),
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("wifi_gpio0", 0, Pins("L2"), IOStandard("LVCMOS33")),
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]
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@ -44,4 +46,4 @@ class Platform(LatticePlatform):
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default_clk_period = 10
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def __init__(self, **kwargs):
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LatticePlatform.__init__(self, "LFE5U-85F-6BG381C", _io, **kwargs)
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LatticePlatform.__init__(self, "LFE5U-45F-6BG381C", _io, **kwargs)
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@ -45,6 +45,12 @@ class _CRG(Module):
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o_Z=new_sdram_ps_clk)
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sdram_ps_clk = new_sdram_ps_clk
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self.comb += self.cd_sys_ps.clk.eq(sdram_ps_clk)
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sdram_clock = platform.request("sdram_clock")
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self.comb += sdram_clock.eq(sdram_ps_clk)
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# Stop ESP32 from resetting FPGA
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wifi_gpio0 = platform.request("wifi_gpio0")
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self.comb += wifi_gpio0.eq(1)
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class BaseSoC(SoCSDRAM):
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@ -13,8 +13,6 @@ from litex.build.lattice import common
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# TODO:
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# - add timing constraint support.
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# - check/document attr_translate.
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# - use constraint file when prjtrellis will support it.
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nextpnr_ecp5_architectures = {
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"lfe5u-25f": "25k",
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@ -29,6 +27,37 @@ nextpnr_ecp5_architectures = {
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}
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def _format_constraint(c):
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if isinstance(c, Pins):
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return ("LOCATE COMP ", " SITE " + "\"" + c.identifiers[0] + "\"")
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elif isinstance(c, IOStandard):
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return ("IOBUF PORT ", " IO_TYPE=" + c.name)
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elif isinstance(c, Misc):
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return c.misc
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def _format_lpf(signame, pin, others, resname):
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fmt_c = [_format_constraint(c) for c in ([Pins(pin)] + others)]
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r = ""
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for pre, suf in fmt_c:
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r += pre + "\"" + signame + "\"" + suf + ";\n"
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return r
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def _build_lpf(named_sc, named_pc):
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r = "BLOCK RESETPATHS;\n"
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r += "BLOCK ASYNCPATHS;\n"
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for sig, pins, others, resname in named_sc:
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if len(pins) > 1:
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for i, p in enumerate(pins):
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r += _format_lpf(sig + "[" + str(i) + "]", p, others, resname)
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else:
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r += _format_lpf(sig, pins[0], others, resname)
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if named_pc:
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r += "\n" + "\n\n".join(named_pc)
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return r
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def yosys_import_sources(platform):
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includes = ""
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reads = []
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@ -40,93 +69,6 @@ def yosys_import_sources(platform):
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return "\n".join(reads)
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def generate_prjtrellis_top(top_file, platform, vns):
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# resolve ios directions / types
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ios, _ = platform.resolve_signals(vns)
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ios_direction = {}
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ios_type = {}
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cm = platform.constraint_manager
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for io_name, io_pins, _, _ in ios:
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for cm_sig, cm_pins, _, _ in cm.get_sig_constraints():
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if io_pins == cm_pins:
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ios_direction[io_name] = cm_sig.direction
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ios_type[io_name] = cm_sig.type
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last_io_name = io_name
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# prjtrellis module / ios declaration
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top_contents = []
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top_contents.append("module prjtrellis_{build_name}(")
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ios_declaration = ""
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for io_name, io_pins, io_others, _ in ios:
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for io_other in io_others:
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if isinstance(io_other, IOStandard):
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io_standard = io_other.name
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for i, io_pin in enumerate(io_pins):
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ios_declaration += "(* LOC=\"{}\" *) (* IO_TYPE=\"{}\" *)\n".format(io_pin, io_standard)
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ios_declaration += "\t" + ios_direction[io_name] + " " + io_name + "_io" + (str(i) if len(io_pins) > 1 else "")
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ios_declaration += ",\n" if io_name != last_io_name or (i != len(io_pins) - 1) else ""
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top_contents.append(ios_declaration)
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top_contents.append(");\n")
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# top signals declaration
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signals_declaration = ""
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for io_name, io_pins, _, _ in ios:
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signals_declaration += ios_type[io_name] + " "
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if len(io_pins) > 1:
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signals_declaration += "[{}:0] ".format(len(io_pins) - 1)
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signals_declaration += io_name
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signals_declaration += ";\n"
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top_contents.append(signals_declaration)
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# trellis_ios declaration
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trellis_io_declaration = ""
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for io_name, io_pins, io_others, _ in ios:
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for i, io_pin in enumerate(io_pins):
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io_suffix = "io" + str(i) if len(io_pins) > 1 else "io"
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if ios_direction[io_name] == "input":
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trellis_io_declaration += \
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"TRELLIS_IO #(.DIR(\"INPUT\")) {} (.B({}), .O({}));\n".format(
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io_name + "_buf" + str(i), io_name + "_" + io_suffix, io_name + "[" + str(i) + "]")
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elif ios_direction[io_name] == "output":
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trellis_io_declaration += \
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"TRELLIS_IO #(.DIR(\"OUTPUT\")) {} (.B({}), .I({}));\n".format(
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io_name + "_buf" + str(i), io_name + "_" + io_suffix, io_name + "[" + str(i) + "]")
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else:
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pass # handled by Migen's Tristate
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top_contents.append(trellis_io_declaration)
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# top_recopy:
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# - skip module definition.
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# - use ios names for inouts.
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def replace_inouts(l):
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r = l
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for io_name, io_pins, _, _ in ios:
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if ios_direction[io_name] == "inout":
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if len(io_pins) > 1:
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for i in range(len(io_pins)):
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r = r.replace(io_name + "[" + str(i) + "]", io_name + "_io" + str(i))
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else:
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r = r.replace(io_name, io_name + "_io")
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return r
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skip = True
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f = open(top_file, "r")
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for l in f:
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if not skip:
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l = l.replace("\n", "")
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l = l.replace("{", "{{")
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l = l.replace("}", "}}")
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l = replace_inouts(l)
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top_contents.append(l)
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if ");" in l:
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skip = False
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f.close()
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top_contents = "\n".join(top_contents)
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return top_contents
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class LatticePrjTrellisToolchain:
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attr_translate = {
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# FIXME: document
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@ -156,22 +98,20 @@ class LatticePrjTrellisToolchain:
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fragment = fragment.get_fragment()
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platform.finalize(fragment)
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top_output = platform.get_verilog(fragment)
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top_output = platform.get_verilog(fragment, name=build_name)
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named_sc, named_pc = platform.resolve_signals(top_output.ns)
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top_file = build_name + ".v"
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top_output.write(top_file)
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platform.add_source(top_file)
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# insert constraints and trellis_io to generated verilog
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prjtrellis_top_file = build_name + "_prjtrellis.v"
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prjtrellis_top_contents = generate_prjtrellis_top(top_file, platform, top_output.ns)
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prjtrellis_top_contents = prjtrellis_top_contents.format(build_name=build_name)
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tools.write_to_file(prjtrellis_top_file, prjtrellis_top_contents)
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platform.add_source(prjtrellis_top_file)
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# generate constraints
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tools.write_to_file(build_name + ".lpf", _build_lpf(named_sc, named_pc))
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# generate yosys script
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yosys_script_file = build_name + ".ys"
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yosys_script_contents = [
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yosys_import_sources(platform),
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"synth_ecp5 -nomux -json {build_name}.json -top prjtrellis_{build_name}"
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"synth_ecp5 -nomux -json {build_name}.json -top {build_name}"
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]
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yosys_script_contents = "\n".join(yosys_script_contents)
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yosys_script_contents = yosys_script_contents.format(build_name=build_name)
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@ -187,7 +127,7 @@ class LatticePrjTrellisToolchain:
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build_script_file = "build_" + build_name + ".sh"
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build_script_contents = [
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"yosys -q -l {build_name}.rpt {build_name}.ys",
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"nextpnr-ecp5 --json {build_name}.json --textcfg {build_name}.config --basecfg {basecfg} --{architecture}",
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"nextpnr-ecp5 --json {build_name}.json --lpf {build_name}.lpf --textcfg {build_name}.config --basecfg {basecfg} --{architecture}",
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"ecppack {build_name}.config {build_name}.bit"
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]
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