fhdl/verilog: Improve code presentation.
- Add a LiteX Header/Trailer. - Add _print_signal function. - Add more infos to the Header. - Add separators between blocks of code. - Align Wire/Reg definition.
This commit is contained in:
Florent Kermarrec
parent
08a9392c54
commit
942e50b992
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@ -44,9 +44,9 @@ def memory_emit_verilog(memory, ns, add_data_file):
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# Memory Description.
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# -------------------
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r += "//" + "-"*80 + "\n"
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r += "//" + "-"*78 + "\n"
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r += f"// Memory {gn(memory)}: {memory.depth}-words x {memory.width}-bit\n"
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r += "//" + "-"*80 + "\n"
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r += "//" + "-"*78 + "\n"
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for n, port in enumerate(memory.ports):
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r += f"// Port {n} | "
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if port.async_read:
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@ -150,6 +150,6 @@ def memory_emit_verilog(memory, ns, add_data_file):
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# Read-First/No-Change mode: Data already Read on Data Register.
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if port.mode in [READ_FIRST, NO_CHANGE]:
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r += f"assign {gn(port.dat_r)} = {gn(data_regs[n])};\n"
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r += "//" + "-"*80 + "\n\n"
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r += "\n\n"
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return r
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@ -13,6 +13,9 @@
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# This file is Copyright (c) 2018 Robin Ole Heinemann <robin.ole.heinemann@t-online.de>
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# SPDX-License-Identifier: BSD-2-Clause
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import time
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import datetime
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from functools import partial
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from operator import itemgetter
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import collections
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@ -24,7 +27,50 @@ from migen.fhdl.namer import build_namespace
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from migen.fhdl.conv_output import ConvOutput
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from migen.fhdl.specials import Memory
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from litex.build.tools import generated_banner
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from litex.build.tools import get_litex_git_revision
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# ------------------------------------------------------------------------------------------------ #
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# BANNER/TRAILER/SEPARATORS #
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# ------------------------------------------------------------------------------------------------ #
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def _print_banner(filename, device):
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return """\
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// -----------------------------------------------------------------------------
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// Auto-Generated by: __ _ __ _ __
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// / / (_) /____ | |/_/
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// / /__/ / __/ -_)> <
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// /____/_/\\__/\\__/_/|_|
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// Build your hardware, easily!
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// https://github.com/enjoy-digital/litex
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//
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// Filename : {filename}.v
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// Device : {device}
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// LiteX sha1 : {revision}
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// Date : {date}
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//------------------------------------------------------------------------------\n
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""".format(
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device = device,
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filename = filename,
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revision = get_litex_git_revision(),
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date = datetime.datetime.fromtimestamp(time.time()).strftime("%Y-%m-%d %H:%M:%S")
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)
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def _print_trailer():
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return """
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// -----------------------------------------------------------------------------
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// Auto-Generated by LiteX on {date}.
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//------------------------------------------------------------------------------
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""".format(
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date=datetime.datetime.fromtimestamp(time.time()).strftime("%Y-%m-%d %H:%M:%S")
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)
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def _print_separator(msg=""):
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r = "\n"
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r += "//" + "-"*78 + "\n"
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r += f"// {msg}\n"
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r += "//" + "-"*78 + "\n"
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r += "\n"
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return r
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# ------------------------------------------------------------------------------------------------ #
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# RESERVED KEYWORDS #
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@ -333,7 +379,8 @@ def _print_module(f, ios, name, ns, attr_translate):
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inouts = list_special_ios(f, ins=False, outs=False, inouts=True)
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targets = list_targets(f) | special_outs
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wires = _list_comb_wires(f) | special_outs
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r = "module " + name + "(\n"
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r = f"module {name} (\n"
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firstp = True
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for sig in sorted(ios, key=lambda x: x.duid):
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if not firstp:
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@ -346,18 +393,29 @@ def _print_module(f, ios, name, ns, attr_translate):
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sig.name = ns.get_name(sig)
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if sig in inouts:
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sig.direction = "inout"
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r += "\tinout wire " + _print_signal(ns, sig)
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r += "\tinout wire " + _print_signal(ns, sig)
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elif sig in targets:
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sig.direction = "output"
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sig.direction = "output "
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if sig in wires:
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r += "\toutput wire " + _print_signal(ns, sig)
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else:
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sig.type = "reg"
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r += "\toutput reg " + _print_signal(ns, sig)
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r += "\toutput reg " + _print_signal(ns, sig)
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else:
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sig.direction = "input"
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r += "\tinput wire " + _print_signal(ns, sig)
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r += "\tinput wire " + _print_signal(ns, sig)
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r += "\n);\n\n"
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return r
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def _print_signals(f, ios, name, ns, attr_translate):
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sigs = list_signals(f) | list_special_ios(f, ins=True, outs=True, inouts=True)
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special_outs = list_special_ios(f, ins=False, outs=True, inouts=True)
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inouts = list_special_ios(f, ins=False, outs=False, inouts=True)
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targets = list_targets(f) | special_outs
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wires = _list_comb_wires(f) | special_outs
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r = ""
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for sig in sorted(sigs - ios, key=lambda x: x.duid):
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attr = _print_attribute(sig.attr, attr_translate)
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if attr:
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@ -365,8 +423,7 @@ def _print_module(f, ios, name, ns, attr_translate):
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if sig in wires:
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r += "wire " + _print_signal(ns, sig) + ";\n"
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else:
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r += "reg " + _print_signal(ns, sig) + " = " + _print_expression(ns, sig.reset)[0] + ";\n"
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r += "\n"
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r += "reg " + _print_signal(ns, sig) + " = " + _print_expression(ns, sig.reset)[0] + ";\n"
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return r
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# ------------------------------------------------------------------------------------------------ #
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@ -525,27 +582,40 @@ def convert(f, ios=set(), name="top", platform=None,
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# Build Verilog.
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# --------------
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verilog = generated_banner("//")
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verilog = ""
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verilog += _print_banner(
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filename = name,
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device = getattr(platform, "device", "Unknown")
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)
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# Module Top.
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# Module Definition.
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verilog += _print_separator("Module")
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verilog += _print_module(f, ios, name, ns, attr_translate)
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# Module Signals.
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verilog += _print_separator("Signals")
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verilog += _print_signals(f, ios, name, ns, attr_translate)
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# Combinatorial Logic.
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verilog += _print_separator("Combinatorial Logic")
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if regular_comb:
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verilog += _print_combinatorial_logic_synth(f, ns)
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else:
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verilog += _print_combinatorial_logic_sim(f, ns)
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# Synchronous Logic.
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verilog += _print_separator("Synchronous Logic")
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verilog += _print_synchronous_logic(f, ns)
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# Specials
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verilog += _print_separator("Specialized Logic")
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verilog += _print_specials(special_overrides, f.specials - lowered_specials,
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ns, r.add_data_file, attr_translate)
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# Module End.
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verilog += "endmodule\n"
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verilog += _print_trailer()
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r.set_main_source(verilog)
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r.ns = ns
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