soc/cores/cpu/zynqmp/core.py: added method to enable ZynqMP UART interface in EMIO mode

litex/soc/cores/cpu/zynqmp/core.py

@@ -51,6 +51,7 @@ class ZynqMP(CPU):
         self.axi_gp_masters = [None] * 3  # General Purpose AXI Masters.
         self.gem_mac        = []          # GEM MAC reserved ports.
         self.i2c_use        = []          # I2c reserved ports.
+        self.uart_use       = []          # UART reserved ports.
 
         self.cd_ps = ClockDomain()
 
@@ -296,6 +297,18 @@ class ZynqMP(CPU):
             f"o_emio_i2c{n}_sda_t" : sda_t,
         })
 
+    def add_uart(self, n, pads):
+        assert n < 2 and not n in self.uart_use
+        assert pads is not None
+
+        self.config[f"PSU__UART{n}__PERIPHERAL__ENABLE"] = 1
+        self.config[f"PSU__UART{n}__PERIPHERAL__IO"]     = "EMIO"
+
+        self.cpu_params.update({
+            f"i_emio_uart{n}_rxd" : pads.rx,
+            f"o_emio_uart{n}_txd" : pads.tx,
+        })
+
     def do_finalize(self):
         if len(self.ps_tcl):
             self.ps_tcl.append("set_property -dict [list \\")