cores/ram: cosmetic cleanup.
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@ -42,12 +42,14 @@ class Up5kSPRAM(Module):
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depth_cascading = size//(128*kB)
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width_cascading = 4
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# Combine RAMs to increase Depth.
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for d in range(depth_cascading):
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# Combine RAMs to increase Width.
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for w in range(width_cascading):
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datain = Signal(16)
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dataout = Signal(16)
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datain = Signal(16)
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dataout = Signal(16)
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maskwren = Signal(4)
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wren = Signal()
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wren = Signal()
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self.comb += [
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datain.eq(self.bus.dat_w[16*w:16*(w+1)]),
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If(self.bus.adr[14:14+log2_int(depth_cascading)+1] == d,
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@ -61,16 +63,16 @@ class Up5kSPRAM(Module):
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maskwren[3].eq(self.bus.sel[2*w + 1]),
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]
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self.specials += Instance("SB_SPRAM256KA",
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i_ADDRESS=self.bus.adr[:14],
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i_DATAIN=datain,
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i_MASKWREN=maskwren,
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i_WREN=wren,
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i_CHIPSELECT=0b1,
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i_CLOCK=ClockSignal("sys"),
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i_STANDBY=0b0,
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i_SLEEP=0b0,
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i_POWEROFF=0b1,
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o_DATAOUT=dataout
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i_CLOCK = ClockSignal("sys"),
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i_STANDBY = 0b0,
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i_SLEEP = 0b0,
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i_POWEROFF = 0b1,
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i_ADDRESS = self.bus.adr[:14],
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i_DATAIN = datain,
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i_MASKWREN = maskwren,
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i_WREN = wren,
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i_CHIPSELECT = 0b1,
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o_DATAOUT = dataout
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)
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self.sync += self.bus.ack.eq(self.bus.stb & self.bus.cyc & ~self.bus.ack)
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@ -36,17 +36,19 @@ class NXLRAM(Module):
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depth_cascading = size//(128*kB)
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width_cascading = 2
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# Combine RAMs to increase Depth.
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for d in range(depth_cascading):
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# Combine RAMs to increase Width.
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for w in range(width_cascading):
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datain = Signal(32)
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datain = Signal(32)
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dataout = Signal(32)
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cs = Signal()
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wren = Signal()
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cs = Signal()
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wren = Signal()
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self.comb += [
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cs.eq(self.bus.adr[14:14+log2_int(depth_cascading)+1] == d),
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wren.eq(self.bus.we & self.bus.stb & self.bus.cyc),
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datain.eq(self.bus.dat_w[32*w:32*(w+1)]),
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If(cs,
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If(self.bus.adr[14:14+log2_int(depth_cascading)+1] == d,
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cs.eq(1),
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wren.eq(self.bus.we & self.bus.stb & self.bus.cyc),
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self.bus.dat_r[32*w:32*(w+1)].eq(dataout)
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),
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]
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