Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

cores/ram: cosmetic cleanup.

This commit is contained in:
Florent Kermarrec 2020-11-18 21:44:53 +01:00
parent 444a605dea
commit 9440975a1f
2 changed files with 23 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
litex/soc/cores/ram/lattice_ice40.py
View File

@ -42,12 +42,14 @@ class Up5kSPRAM(Module):
depth_cascading = size//(128*kB) depth_cascading = size//(128*kB)
width_cascading = 4 width_cascading = 4
# Combine RAMs to increase Depth.
for d in range(depth_cascading): for d in range(depth_cascading):
# Combine RAMs to increase Width.
for w in range(width_cascading): for w in range(width_cascading):
datain = Signal(16) datain = Signal(16)
dataout = Signal(16) dataout = Signal(16)
maskwren = Signal(4) maskwren = Signal(4)
wren = Signal() wren = Signal()
self.comb += [ self.comb += [
datain.eq(self.bus.dat_w[16*w:16*(w+1)]), datain.eq(self.bus.dat_w[16*w:16*(w+1)]),
If(self.bus.adr[14:14+log2_int(depth_cascading)+1] == d, If(self.bus.adr[14:14+log2_int(depth_cascading)+1] == d,
@ -61,16 +63,16 @@ class Up5kSPRAM(Module):
maskwren[3].eq(self.bus.sel[2*w + 1]), maskwren[3].eq(self.bus.sel[2*w + 1]),
] ]
self.specials += Instance("SB_SPRAM256KA", self.specials += Instance("SB_SPRAM256KA",
i_ADDRESS=self.bus.adr[:14], i_CLOCK = ClockSignal("sys"),
i_DATAIN=datain, i_STANDBY = 0b0,
i_MASKWREN=maskwren, i_SLEEP = 0b0,
i_WREN=wren, i_POWEROFF = 0b1,
i_CHIPSELECT=0b1, i_ADDRESS = self.bus.adr[:14],
i_CLOCK=ClockSignal("sys"), i_DATAIN = datain,
i_STANDBY=0b0, i_MASKWREN = maskwren,
i_SLEEP=0b0, i_WREN = wren,
i_POWEROFF=0b1, i_CHIPSELECT = 0b1,
o_DATAOUT=dataout o_DATAOUT = dataout
) )
self.sync += self.bus.ack.eq(self.bus.stb & self.bus.cyc & ~self.bus.ack) self.sync += self.bus.ack.eq(self.bus.stb & self.bus.cyc & ~self.bus.ack)

14
litex/soc/cores/ram/lattice_nx.py
View File

@ -36,17 +36,19 @@ class NXLRAM(Module):
depth_cascading = size//(128*kB) depth_cascading = size//(128*kB)
width_cascading = 2 width_cascading = 2
# Combine RAMs to increase Depth.
for d in range(depth_cascading): for d in range(depth_cascading):
# Combine RAMs to increase Width.
for w in range(width_cascading): for w in range(width_cascading):
datain = Signal(32) datain = Signal(32)
dataout = Signal(32) dataout = Signal(32)
cs = Signal() cs = Signal()
wren = Signal() wren = Signal()
self.comb += [ self.comb += [
cs.eq(self.bus.adr[14:14+log2_int(depth_cascading)+1] == d),
wren.eq(self.bus.we & self.bus.stb & self.bus.cyc),
datain.eq(self.bus.dat_w[32*w:32*(w+1)]), datain.eq(self.bus.dat_w[32*w:32*(w+1)]),
If(cs, If(self.bus.adr[14:14+log2_int(depth_cascading)+1] == d,
cs.eq(1),
wren.eq(self.bus.we & self.bus.stb & self.bus.cyc),
self.bus.dat_r[32*w:32*(w+1)].eq(dataout) self.bus.dat_r[32*w:32*(w+1)].eq(dataout)
), ),
] ]