test/fifo: convert to new API

This commit is contained in:
Sebastien Bourdeauducq 2015-09-19 23:20:30 +08:00
parent dcf4f7fef3
commit 944a0b0480
1 changed files with 32 additions and 27 deletions

View File

@ -1,13 +1,14 @@
import unittest import unittest
from itertools import count
from migen import * from migen import *
from migen.genlib.fifo import SyncFIFO from migen.genlib.fifo import SyncFIFO
from migen.test.support import SimCase, SimBench from migen.test.support import SimCase
class SyncFIFOCase(SimCase, unittest.TestCase): class SyncFIFOCase(SimCase, unittest.TestCase):
class TestBench(SimBench): class TestBench(Module):
def __init__(self): def __init__(self):
self.submodules.dut = SyncFIFO([("a", 32), ("b", 32)], 2) self.submodules.dut = SyncFIFO([("a", 32), ("b", 32)], 2)
@ -24,31 +25,35 @@ class SyncFIFOCase(SimCase, unittest.TestCase):
def test_run_sequence(self): def test_run_sequence(self):
seq = list(range(20)) seq = list(range(20))
def cb(tb, tbp): def gen():
for cycle in count():
# fire re and we at "random" # fire re and we at "random"
tbp.dut.we = tbp.simulator.cycle_counter % 2 == 0 yield self.tb.dut.we, cycle % 2 == 0
tbp.dut.re = tbp.simulator.cycle_counter % 3 == 0 yield self.tb.dut.re, cycle % 3 == 0
# the output if valid must be correct # the output if valid must be correct
if tbp.dut.readable and tbp.dut.re: if (yield self.tb.dut.readable) and (yield self.tb.dut.re):
try: try:
i = seq.pop(0) i = seq.pop(0)
except IndexError: except IndexError:
raise StopSimulation break
self.assertEqual(tbp.dut.dout.a, i) self.assertEqual((yield self.tb.dut.dout.a), i)
self.assertEqual(tbp.dut.dout.b, i*2) self.assertEqual((yield self.tb.dut.dout.b), i*2)
self.run_with(cb) yield
self.run_with(gen())
def test_replace(self): def test_replace(self):
seq = [x for x in range(20) if x % 5] seq = [x for x in range(20) if x % 5]
def cb(tb, tbp): def gen():
tbp.dut.we = tbp.simulator.cycle_counter % 2 == 0 for cycle in count():
tbp.dut.re = tbp.simulator.cycle_counter % 3 == 0 yield self.tb.dut.we, cycle % 2 == 0
tbp.dut.replace = tbp.dut.din.a % 5 == 1 yield self.tb.dut.re, cycle % 7 == 0
if tbp.dut.readable and tbp.dut.re: yield self.tb.dut.replace, (yield self.tb.dut.din.a) % 5 == 1
if (yield self.tb.dut.readable) and (yield self.tb.dut.re):
try: try:
i = seq.pop(0) i = seq.pop(0)
except IndexError: except IndexError:
raise StopSimulation break
self.assertEqual(tbp.dut.dout.a, i) self.assertEqual((yield self.tb.dut.dout.a), i)
self.assertEqual(tbp.dut.dout.b, i*2) self.assertEqual((yield self.tb.dut.dout.b), i*2)
self.run_with(cb) yield
self.run_with(gen())