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tools/litex_sim: use similar analyzer configuration than wiki.

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This commit is contained in:
Florent Kermarrec 2020-04-27 15:08:48 +02:00
parent 443cc72d0a
commit 9460e048ec
1 changed files with 12 additions and 3 deletions
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15
litex/tools/litex_sim.py
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@ -270,10 +270,19 @@ class SimSoC(SoCSDRAM):
# Analyzer ---------------------------------------------------------------------------------
if with_analyzer:
analyzer_signals = [
self.cpu.ibus,
self.cpu.dbus
self.cpu.ibus.stb,
self.cpu.ibus.cyc,
self.cpu.ibus.adr,
self.cpu.ibus.we,
self.cpu.ibus.ack,
self.cpu.ibus.sel,
self.cpu.ibus.dat_w,
self.cpu.ibus.dat_r,
]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 512)
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
depth = 512,
clock_domain = "sys",
csr_csv = "analyzer.csv")
self.add_csr("analyzer")
# Build --------------------------------------------------------------------------------------------