cpu/openc906: fix the semantics of self.reset

LiteX defaults to active-high reset signals, but OpenC906 uses
active-low ones, and the self.reset signal of openc906 module is wrongly
wired that it will force the CPU to run instead of force it to reset
(because it is ORed and then feed to the active-low reset line).

Fix this by using AND and inverting self.reset.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>

litex/soc/cores/cpu/openc906/core.py

@@ -93,7 +93,7 @@ class OpenC906(CPU):
         self.cpu_params = dict(
             # Clk / Rst.
             i_pll_core_cpuclk  = ClockSignal("sys"),
-            i_pad_cpu_rst_b    = ~ResetSignal("sys") | self.reset,
+            i_pad_cpu_rst_b    = ~ResetSignal("sys") & ~self.reset,
             i_axim_clk_en      = 1,
 
             # Debug (ignored).