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cpu/openc906: fix the semantics of self.reset 

LiteX defaults to active-high reset signals, but OpenC906 uses
active-low ones, and the self.reset signal of openc906 module is wrongly
wired that it will force the CPU to run instead of force it to reset
(because it is ORed and then feed to the active-low reset line).

Fix this by using AND and inverting self.reset.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
This commit is contained in:
Icenowy Zheng 2022-11-07 11:51:38 +08:00
parent 38ee44a85a
commit 9493338c68
1 changed files with 1 additions and 1 deletions
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2
litex/soc/cores/cpu/openc906/core.py
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@ -93,7 +93,7 @@ class OpenC906(CPU):
self.cpu_params = dict( self.cpu_params = dict(
# Clk / Rst. # Clk / Rst.
i_pll_core_cpuclk = ClockSignal("sys"), i_pll_core_cpuclk = ClockSignal("sys"),
i_pad_cpu_rst_b = ~ResetSignal("sys") | self.reset, i_pad_cpu_rst_b = ~ResetSignal("sys") & ~self.reset,
i_axim_clk_en = 1, i_axim_clk_en = 1,
# Debug (ignored). # Debug (ignored).