corelogic: fix signal exports

migen/corelogic/divider.py

@@ -4,12 +4,12 @@ class Inst:
 	def __init__(self, w):
 		self.w = w
 		
-		start_i = Signal()
+		self.start_i = Signal()
-		dividend_i = Signal(BV(w))
+		self.dividend_i = Signal(BV(w))
-		divisor_i = Signal(BV(w))
+		self.divisor_i = Signal(BV(w))
-		ready_o = Signal()
+		self.ready_o = Signal()
-		quotient_o = Signal(BV(w))
+		self.quotient_o = Signal(BV(w))
-		remainder_o = Signal(BV(w))
+		self.remainder_o = Signal(BV(w))
 	
 	def get_fragment(self):
 		w = self.w

migen/corelogic/roundrobin.py

@@ -4,8 +4,8 @@ class Inst:
 	def __init__(self, n):
 		self.n = n
 		self.bn = bits_for(self.n-1)
-		request = Signal(BV(self.n))
+		self.request = Signal(BV(self.n))
-		grant = Signal(BV(self.bn))
+		self.grant = Signal(BV(self.bn))
 	
 	def get_fragment(self):
 		cases = []