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vivado: add support for pre_synthesis_commands

This commit is contained in:
Robert Jordens 2015-04-03 14:55:22 -06:00 committed by Sebastien Bourdeauducq
parent 4522956f11
commit 9506f69390
1 changed files with 2 additions and 0 deletions
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2
mibuild/xilinx/vivado.py
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@ -69,6 +69,7 @@ class XilinxVivadoToolchain:
def __init__(self):
self.bitstream_commands = []
self.additional_commands = []
self.pre_synthesis_commands = []
def _build_batch(self, platform, sources, build_name):
tcl = []
@ -76,6 +77,7 @@ class XilinxVivadoToolchain:
tcl.append("add_files " + filename.replace("\\", "/"))
tcl.append("read_xdc %s.xdc" %build_name)
tcl.extend(c.format(build_name=build_name) for c in self.pre_synthesis_commands)
tcl.append("synth_design -top top -part %s -include_dirs {%s}" %(platform.device, " ".join(platform.verilog_include_paths)))
tcl.append("report_utilization -hierarchical -file %s_utilization_hierarchical_synth.rpt" %(build_name))
tcl.append("report_utilization -file %s_utilization_synth.rpt" %(build_name))