framebuffer: use new flow API
This commit is contained in:
Sebastien Bourdeauducq
parent
3be20f6ae4
commit
950d3a4469
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@ -55,10 +55,9 @@ class _FrameInitiator(spi.SingleGenerator):
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]
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spi.SingleGenerator.__init__(self, layout, spi.MODE_CONTINUOUS)
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class VTG(Module, Actor):
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class VTG(Module):
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def __init__(self):
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Actor.__init__(self,
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("timing", Sink, [
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self.timing = Sink([
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("hres", _hbits),
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("hsync_start", _hbits),
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("hsync_end", _hbits),
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@ -66,10 +65,10 @@ class VTG(Module, Actor):
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("vres", _vbits),
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("vsync_start", _vbits),
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("vsync_end", _vbits),
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("vscan", _vbits)]),
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("pixels", Sink, _pixel_layout),
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("dac", Source, _dac_layout)
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)
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("vscan", _vbits)])
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self.pixels = Sink(_pixel_layout)
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self.dac = Source(_dac_layout)
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self.busy = Signal()
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hactive = Signal()
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vactive = Signal()
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@ -83,29 +82,30 @@ class VTG(Module, Actor):
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self.comb += [
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active.eq(hactive & vactive),
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If(active,
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[getattr(getattr(self.token("dac"), p), c).eq(getattr(getattr(self.token("pixels"), p), c)[skip:])
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[getattr(getattr(self.dac.payload, p), c).eq(getattr(getattr(self.pixels.payload, p), c)[skip:])
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for p in ["p0", "p1"] for c in ["r", "g", "b"]]
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),
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generate_en.eq(self.endpoints["timing"].stb & (~active | self.endpoints["pixels"].stb)),
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self.endpoints["pixels"].ack.eq(self.endpoints["dac"].ack & active),
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self.endpoints["dac"].stb.eq(generate_en)
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generate_en.eq(self.timing.stb & (~active | self.pixels.stb)),
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self.pixels.ack.eq(self.dac.ack & active),
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self.dac.stb.eq(generate_en),
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self.busy.eq(generate_en)
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]
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tp = self.token("timing")
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tp = self.timing.payload
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self.sync += [
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self.endpoints["timing"].ack.eq(0),
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If(generate_en & self.endpoints["dac"].ack,
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self.timing.ack.eq(0),
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If(generate_en & self.dac.ack,
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hcounter.eq(hcounter + 1),
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If(hcounter == 0, hactive.eq(1)),
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If(hcounter == tp.hres, hactive.eq(0)),
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If(hcounter == tp.hsync_start, self.token("dac").hsync.eq(1)),
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If(hcounter == tp.hsync_end, self.token("dac").hsync.eq(0)),
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If(hcounter == tp.hsync_start, self.dac.payload.hsync.eq(1)),
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If(hcounter == tp.hsync_end, self.dac.payload.hsync.eq(0)),
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If(hcounter == tp.hscan,
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hcounter.eq(0),
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If(vcounter == tp.vscan,
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vcounter.eq(0),
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self.endpoints["timing"].ack.eq(1)
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self.timing.ack.eq(1)
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).Else(
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vcounter.eq(vcounter + 1)
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)
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@ -113,14 +113,15 @@ class VTG(Module, Actor):
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If(vcounter == 0, vactive.eq(1)),
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If(vcounter == tp.vres, vactive.eq(0)),
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If(vcounter == tp.vsync_start, self.token("dac").vsync.eq(1)),
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If(vcounter == tp.vsync_end, self.token("dac").vsync.eq(0))
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If(vcounter == tp.vsync_start, self.dac.payload.vsync.eq(1)),
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If(vcounter == tp.vsync_end, self.dac.payload.vsync.eq(0))
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)
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]
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class FIFO(Module, Actor):
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class FIFO(Module):
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def __init__(self):
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Actor.__init__(self, ("dac", Sink, _dac_layout))
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self.dac = Sink(_dac_layout)
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self.busy = Signal()
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self.vga_hsync_n = Signal()
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self.vga_vsync_n = Signal()
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@ -151,13 +152,13 @@ class FIFO(Module, Actor):
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Instance.Input("clk_write", ClockSignal()),
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Instance.Input("rst", 0))
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fifo_in = self.token("dac")
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fifo_in = self.dac.payload
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fifo_out = Record(_dac_layout)
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self.comb += [
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self.endpoints["dac"].ack.eq(~fifo_full),
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fifo_write_en.eq(self.endpoints["dac"].stb),
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fifo_data_in.eq(Cat(*fifo_in.flatten())),
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Cat(*fifo_out.flatten()).eq(fifo_data_out),
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self.dac.ack.eq(~fifo_full),
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fifo_write_en.eq(self.dac.stb),
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fifo_data_in.eq(fifo_in.raw_bits()),
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fifo_out.raw_bits().eq(fifo_data_out),
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self.busy.eq(0)
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]
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@ -193,7 +194,7 @@ class Framebuffer(Module):
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pack_factor = asmiport.hub.dw//(2*_bpp)
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packed_pixels = structuring.pack_layout(_pixel_layout, pack_factor)
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fi = _FrameInitiator(asmi_bits, length_bits, alignment_bits)
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self._fi = fi = _FrameInitiator(asmi_bits, length_bits, alignment_bits)
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adrloop = misc.IntSequence(length_bits, asmi_bits)
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adrbuffer = AbstractActor(plumbing.Buffer)
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dma = dma_asmi.Reader(asmiport)
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@ -218,9 +219,7 @@ class Framebuffer(Module):
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"hres", "hsync_start", "hsync_end", "hscan",
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"vres", "vsync_start", "vsync_end", "vscan"])
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g.add_connection(vtg, fifo)
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self.submodules._comp_actor = CompositeActor(g, debugger=False)
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self._csrs = fi.get_csrs() + self._comp_actor.get_csrs()
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self.submodules._comp_actor = CompositeActor(g)
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# Drive pads
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if not simulation:
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@ -234,4 +233,4 @@ class Framebuffer(Module):
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self.comb += pads.psave_n.eq(1)
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def get_csrs(self):
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return self._csrs
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return self._fi.get_csrs()
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