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clock/efinix_trion: Minor cleanup, revert support to None cd in create_clkout.

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This commit is contained in:
Florent Kermarrec 2021-11-08 18:19:12 +01:00
parent af5167c7f0
commit 95a68609cd
1 changed files with 13 additions and 12 deletions
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25
litex/soc/cores/clock/efinix_trion.py
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@ -39,7 +39,7 @@ class TRIONPLL(Module):
self.comb += self.platform.add_iface_io(self.pll_name + "_rstn").eq(~self.reset) self.comb += self.platform.add_iface_io(self.pll_name + "_rstn").eq(~self.reset)
self.comb += self.locked.eq(self.platform.add_iface_io(self.pll_name + "_locked")) self.comb += self.locked.eq(self.platform.add_iface_io(self.pll_name + "_locked"))
def register_clkin(self, clkin, freq, name= ""): def register_clkin(self, clkin, freq, name=""):
block = self.platform.toolchain.ifacewriter.get_block(self.pll_name) block = self.platform.toolchain.ifacewriter.get_block(self.pll_name)
block["input_clock_name"] = self.platform.get_pin_name(clkin) block["input_clock_name"] = self.platform.get_pin_name(clkin)
@ -64,15 +64,15 @@ class TRIONPLL(Module):
self.logger.error("Cannot find a pll with {} as input".format(pad_name)) self.logger.error("Cannot find a pll with {} as input".format(pad_name))
quit() quit()
block["input_clock"] = "EXTERNAL" block["input_clock"] = "EXTERNAL"
block["input_clock_pad"] = pin_name block["input_clock_pad"] = pin_name
block["resource"] = pll_res block["resource"] = pll_res
block["clock_no"] = clock_no block["clock_no"] = clock_no
self.logger.info("Clock source: {}, using EXT_CLK{}".format(block["input_clock"], clock_no)) self.logger.info("Clock source: {}, using EXT_CLK{}".format(block["input_clock"], clock_no))
self.platform.get_pll_resource(pll_res) self.platform.get_pll_resource(pll_res)
else: else:
block["input_clock"] = "INTERNAL" block["input_clock"] = "INTERNAL"
block["resource"] = self.platform.get_free_pll_resource() block["resource"] = self.platform.get_free_pll_resource()
block["input_signal"] = name block["input_signal"] = name
self.logger.info("Clock source: {}".format(block["input_clock"])) self.logger.info("Clock source: {}".format(block["input_clock"]))
@ -85,12 +85,13 @@ class TRIONPLL(Module):
clk_out_name = "{}_CLKOUT{}".format(self.pll_name, self.nclkouts) clk_out_name = "{}_CLKOUT{}".format(self.pll_name, self.nclkouts)
self.platform.add_extension([(clk_out_name, 0, Pins(1))]) if cd is not None:
self.comb += cd.clk.eq(self.platform.request(clk_out_name)) self.platform.add_extension([(clk_out_name, 0, Pins(1))])
if with_reset: self.comb += cd.clk.eq(self.platform.request(clk_out_name))
self.specials += AsyncResetSynchronizer(cd, ~self.locked) if with_reset:
self.platform.toolchain.excluded_ios.append(clk_out_name) self.specials += AsyncResetSynchronizer(cd, ~self.locked)
create_clkout_log(self.logger, cd.name, freq, margin, self.nclkouts) self.platform.toolchain.excluded_ios.append(clk_out_name)
create_clkout_log(self.logger, cd.name, freq, margin, self.nclkouts)
self.nclkouts += 1 self.nclkouts += 1