uart2wishbone: fix missing payload.d
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@ -189,7 +189,7 @@ class UART2Wishbone(Module, AutoCSR):
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)
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),
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uart.tx.sink.stb.eq(1),
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chooser(data, word_cnt.value, uart.tx.sink.d, n=4, reverse=True)
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chooser(data, word_cnt.value, uart.tx.sink.payload.d, n=4, reverse=True)
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)
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###
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