soc_core: Move methods that are no longer recommended to compat_soc_core and add compat_notice to them.

These methods were already a compatibility layer for SoC/LiteXSoC and are not recommended
in new designs.

litex/compat/soc_core.py

@@ -0,0 +1,96 @@
+####################################################################################################
+#       DISCLAIMER: Provides retro-compatibility layer for SoCCore deprecated methods.
+#              Will soon no longer work, please don't use in new designs.
+####################################################################################################
+
+#
+# This file is part of LiteX.
+#
+# This file is Copyright (c) 2013-2014 Sebastien Bourdeauducq <sb@m-labs.hk>
+# This file is Copyright (c) 2014-2019 Florent Kermarrec <florent@enjoy-digital.fr>
+# This file is Copyright (c) 2018 Dolu1990 <charles.papon.90@gmail.com>
+# This file is Copyright (c) 2019 Gabriel L. Somlo <gsomlo@gmail.com>
+# This file is Copyright (c) 2019 Ilia Sergachev <ilia.sergachev@protonmail.ch>
+# This file is Copyright (c) 2018 Jean-François Nguyen <jf@lambdaconcept.fr>
+# This file is Copyright (c) 2020 Raptor Engineering, LLC <sales@raptorengineering.com>
+# This file is Copyright (c) 2015 Robert Jordens <jordens@gmail.com>
+# This file is Copyright (c) 2018 Sean Cross <sean@xobs.io>
+# This file is Copyright (c) 2018 Stafford Horne <shorne@gmail.com>
+# This file is Copyright (c) 2018-2017 Tim 'mithro' Ansell <me@mith.ro>
+# This file is Copyright (c) 2015 whitequark <whitequark@whitequark.org>
+# This file is Copyright (c) 2014 Yann Sionneau <ys@m-labs.hk>
+# SPDX-License-Identifier: BSD-2-Clause
+
+from migen import *
+
+
+from litex.compat import compat_notice
+from litex.soc.integration.soc import *
+
+__all__ = [
+    "mem_decoder",
+    "SoCCoreCompat",
+]
+
+# Helpers ------------------------------------------------------------------------------------------
+
+def mem_decoder(address, size=0x10000000):
+    size = 2**log2_int(size, False)
+    assert (address & (size - 1)) == 0
+    address >>= 2 # bytes to words aligned
+    size    >>= 2 # bytes to words aligned
+    return lambda a: (a[log2_int(size):] == (address >> log2_int(size)))
+
+# SoCCoreCompat -------------------------------------------------------------------------------------
+
+class SoCCoreCompat:
+    # Methods --------------------------------------------------------------------------------------
+    def add_interrupt(self, interrupt_name, interrupt_id=None, use_loc_if_exists=False):
+        compat_notice("SoCCore.add_interrupt", date="2022-11-03", info="Switch to SoC.irq.add(...)")
+        self.irq.add(interrupt_name, interrupt_id, use_loc_if_exists=use_loc_if_exists)
+
+    def add_wb_master(self, wbm):
+        compat_notice("SoCCore.add_wb_master", date="2022-11-03", info="Switch to SoC.bus.add_master(...).")
+        self.bus.add_master(master=wbm)
+
+    def add_wb_slave(self, address, interface, size=None):
+        compat_notice("SoCCore.add_wb_slave", date="2022-11-03", info="Switch to SoC.bus.add_slave(...).")
+        wb_name = None
+        for name, region in self.bus.regions.items():
+            if address == region.origin:
+                wb_name = name
+                break
+        if wb_name is None:
+            self.wb_slaves[address] = interface
+        else:
+            self.bus.add_slave(name=wb_name, slave=interface)
+
+    def register_mem(self, name, address, interface, size=0x10000000):
+        compat_notice("SoCCore.register_mem", date="2022-11-03", info="Switch to SoC.bus.add_slave(...)")
+        self.bus.add_slave(name, interface, SoCRegion(origin=address, size=size))
+
+    def register_rom(self, interface, rom_size=0xa000):
+        compat_notice("SoCCore.register_mem", date="2022-11-03", info="Switch to SoC.bus.add_slave(...)")
+        self.bus.add_slave("rom", interface, SoCRegion(origin=self.cpu.reset_address, size=rom_size))
+
+    # Finalization ---------------------------------------------------------------------------------
+
+    def do_finalize(self):
+        # Retro-compatibility
+        for address, interface in self.wb_slaves.items():
+            wb_name = None
+            for name, region in self.bus.regions.items():
+                if address == region.origin:
+                    wb_name = name
+                    break
+            self.bus.add_slave(name=wb_name, slave=interface)
+        SoC.do_finalize(self)
+        # Retro-compatibility
+        for region in self.bus.regions.values():
+            region.length = region.size
+            region.type   = "cached" if region.cached else "io"
+            if region.linker:
+                region.type += "+linker"
+        self.csr_regions = self.csr.regions
+        for name, value in self.config.items():
+            self.add_config(name, value)

litex/soc/integration/soc_core.py

@@ -26,6 +26,8 @@ from litex.soc.interconnect import wishbone
 from litex.soc.integration.common import *
 from litex.soc.integration.soc import *
 
+from litex.compat.soc_core import *
+
 __all__ = [
     "mem_decoder",
     "get_mem_data",
@@ -37,18 +39,9 @@ __all__ = [
     "soc_mini_argdict",
 ]
 
-# Helpers ------------------------------------------------------------------------------------------
-
-def mem_decoder(address, size=0x10000000):
-    size = 2**log2_int(size, False)
-    assert (address & (size - 1)) == 0
-    address >>= 2 # bytes to words aligned
-    size    >>= 2 # bytes to words aligned
-    return lambda a: (a[log2_int(size):] == (address >> log2_int(size)))
-
 # SoCCore ------------------------------------------------------------------------------------------
 
-class SoCCore(LiteXSoC):
+class SoCCore(LiteXSoC, SoCCoreCompat):
     # Default register/interrupt/memory mappings (can be redefined by user)
     csr_map       = {}
     interrupt_map = {}
@@ -239,65 +232,23 @@ class SoCCore(LiteXSoC):
 
     # Methods --------------------------------------------------------------------------------------
 
-    def add_interrupt(self, interrupt_name, interrupt_id=None, use_loc_if_exists=False):
-        self.irq.add(interrupt_name, interrupt_id, use_loc_if_exists=use_loc_if_exists)
-
     def add_csr(self, csr_name, csr_id=None, use_loc_if_exists=False):
         self.csr.add(csr_name, csr_id, use_loc_if_exists=use_loc_if_exists)
 
     def initialize_rom(self, data):
         self.init_rom(name="rom", contents=data)
 
-    def add_wb_master(self, wbm):
-        self.bus.add_master(master=wbm)
-
-    def add_wb_slave(self, address, interface, size=None):
-        wb_name = None
-        for name, region in self.bus.regions.items():
-            if address == region.origin:
-                wb_name = name
-                break
-        if wb_name is None:
-            self.wb_slaves[address] = interface
-        else:
-            self.bus.add_slave(name=wb_name, slave=interface)
-
     def add_memory_region(self, name, origin, length, type="cached"):
         self.bus.add_region(name, SoCRegion(origin=origin, size=length,
             cached="cached" in type,
-            linker="linker" in type))
+            linker="linker" in type)
-
+        )
-    def register_mem(self, name, address, interface, size=0x10000000):
-        self.bus.add_slave(name, interface, SoCRegion(origin=address, size=size))
-
-    def register_rom(self, interface, rom_size=0xa000):
-        self.bus.add_slave("rom", interface, SoCRegion(origin=self.cpu.reset_address, size=rom_size))
 
     def add_csr_region(self, name, origin, busword, obj):
         self.csr_regions[name] = SoCCSRRegion(origin, busword, obj)
 
-    # Finalization ---------------------------------------------------------------------------------
-
     def do_finalize(self):
-        # Retro-compatibility
+        SoCCoreCompat.do_finalize(self)
-        for address, interface in self.wb_slaves.items():
-            wb_name = None
-            for name, region in self.bus.regions.items():
-                if address == region.origin:
-                    wb_name = name
-                    break
-            self.bus.add_slave(name=wb_name, slave=interface)
-
-        SoC.do_finalize(self)
-        # Retro-compatibility
-        for region in self.bus.regions.values():
-            region.length = region.size
-            region.type   = "cached" if region.cached else "io"
-            if region.linker:
-                region.type += "+linker"
-        self.csr_regions = self.csr.regions
-        for name, value in self.config.items():
-            self.add_config(name, value)
 
 # SoCCore arguments --------------------------------------------------------------------------------