soc_core: Move methods that are no longer recommended to compat_soc_core and add compat_notice to them.
These methods were already a compatibility layer for SoC/LiteXSoC and are not recommended in new designs.
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####################################################################################################
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# DISCLAIMER: Provides retro-compatibility layer for SoCCore deprecated methods.
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# Will soon no longer work, please don't use in new designs.
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####################################################################################################
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#
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# This file is part of LiteX.
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#
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# This file is Copyright (c) 2013-2014 Sebastien Bourdeauducq <sb@m-labs.hk>
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# This file is Copyright (c) 2014-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# This file is Copyright (c) 2018 Dolu1990 <charles.papon.90@gmail.com>
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# This file is Copyright (c) 2019 Gabriel L. Somlo <gsomlo@gmail.com>
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# This file is Copyright (c) 2019 Ilia Sergachev <ilia.sergachev@protonmail.ch>
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# This file is Copyright (c) 2018 Jean-François Nguyen <jf@lambdaconcept.fr>
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# This file is Copyright (c) 2020 Raptor Engineering, LLC <sales@raptorengineering.com>
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# This file is Copyright (c) 2015 Robert Jordens <jordens@gmail.com>
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# This file is Copyright (c) 2018 Sean Cross <sean@xobs.io>
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# This file is Copyright (c) 2018 Stafford Horne <shorne@gmail.com>
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# This file is Copyright (c) 2018-2017 Tim 'mithro' Ansell <me@mith.ro>
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# This file is Copyright (c) 2015 whitequark <whitequark@whitequark.org>
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# This file is Copyright (c) 2014 Yann Sionneau <ys@m-labs.hk>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from litex.compat import compat_notice
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from litex.soc.integration.soc import *
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__all__ = [
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"mem_decoder",
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"SoCCoreCompat",
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]
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# Helpers ------------------------------------------------------------------------------------------
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def mem_decoder(address, size=0x10000000):
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size = 2**log2_int(size, False)
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assert (address & (size - 1)) == 0
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address >>= 2 # bytes to words aligned
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size >>= 2 # bytes to words aligned
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return lambda a: (a[log2_int(size):] == (address >> log2_int(size)))
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# SoCCoreCompat -------------------------------------------------------------------------------------
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class SoCCoreCompat:
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# Methods --------------------------------------------------------------------------------------
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def add_interrupt(self, interrupt_name, interrupt_id=None, use_loc_if_exists=False):
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compat_notice("SoCCore.add_interrupt", date="2022-11-03", info="Switch to SoC.irq.add(...)")
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self.irq.add(interrupt_name, interrupt_id, use_loc_if_exists=use_loc_if_exists)
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def add_wb_master(self, wbm):
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compat_notice("SoCCore.add_wb_master", date="2022-11-03", info="Switch to SoC.bus.add_master(...).")
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self.bus.add_master(master=wbm)
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def add_wb_slave(self, address, interface, size=None):
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compat_notice("SoCCore.add_wb_slave", date="2022-11-03", info="Switch to SoC.bus.add_slave(...).")
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wb_name = None
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for name, region in self.bus.regions.items():
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if address == region.origin:
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wb_name = name
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break
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if wb_name is None:
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self.wb_slaves[address] = interface
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else:
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self.bus.add_slave(name=wb_name, slave=interface)
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def register_mem(self, name, address, interface, size=0x10000000):
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compat_notice("SoCCore.register_mem", date="2022-11-03", info="Switch to SoC.bus.add_slave(...)")
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self.bus.add_slave(name, interface, SoCRegion(origin=address, size=size))
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def register_rom(self, interface, rom_size=0xa000):
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compat_notice("SoCCore.register_mem", date="2022-11-03", info="Switch to SoC.bus.add_slave(...)")
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self.bus.add_slave("rom", interface, SoCRegion(origin=self.cpu.reset_address, size=rom_size))
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# Finalization ---------------------------------------------------------------------------------
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def do_finalize(self):
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# Retro-compatibility
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for address, interface in self.wb_slaves.items():
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wb_name = None
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for name, region in self.bus.regions.items():
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if address == region.origin:
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wb_name = name
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break
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self.bus.add_slave(name=wb_name, slave=interface)
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SoC.do_finalize(self)
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# Retro-compatibility
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for region in self.bus.regions.values():
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region.length = region.size
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region.type = "cached" if region.cached else "io"
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if region.linker:
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region.type += "+linker"
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self.csr_regions = self.csr.regions
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for name, value in self.config.items():
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self.add_config(name, value)
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@ -26,6 +26,8 @@ from litex.soc.interconnect import wishbone
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from litex.soc.integration.common import *
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from litex.soc.integration.common import *
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from litex.soc.integration.soc import *
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from litex.soc.integration.soc import *
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from litex.compat.soc_core import *
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__all__ = [
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__all__ = [
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"mem_decoder",
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"mem_decoder",
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"get_mem_data",
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"get_mem_data",
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@ -37,18 +39,9 @@ __all__ = [
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"soc_mini_argdict",
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"soc_mini_argdict",
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]
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]
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# Helpers ------------------------------------------------------------------------------------------
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def mem_decoder(address, size=0x10000000):
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size = 2**log2_int(size, False)
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assert (address & (size - 1)) == 0
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address >>= 2 # bytes to words aligned
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size >>= 2 # bytes to words aligned
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return lambda a: (a[log2_int(size):] == (address >> log2_int(size)))
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# SoCCore ------------------------------------------------------------------------------------------
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# SoCCore ------------------------------------------------------------------------------------------
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class SoCCore(LiteXSoC):
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class SoCCore(LiteXSoC, SoCCoreCompat):
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# Default register/interrupt/memory mappings (can be redefined by user)
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# Default register/interrupt/memory mappings (can be redefined by user)
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csr_map = {}
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csr_map = {}
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interrupt_map = {}
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interrupt_map = {}
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@ -239,65 +232,23 @@ class SoCCore(LiteXSoC):
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# Methods --------------------------------------------------------------------------------------
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# Methods --------------------------------------------------------------------------------------
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def add_interrupt(self, interrupt_name, interrupt_id=None, use_loc_if_exists=False):
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self.irq.add(interrupt_name, interrupt_id, use_loc_if_exists=use_loc_if_exists)
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def add_csr(self, csr_name, csr_id=None, use_loc_if_exists=False):
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def add_csr(self, csr_name, csr_id=None, use_loc_if_exists=False):
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self.csr.add(csr_name, csr_id, use_loc_if_exists=use_loc_if_exists)
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self.csr.add(csr_name, csr_id, use_loc_if_exists=use_loc_if_exists)
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def initialize_rom(self, data):
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def initialize_rom(self, data):
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self.init_rom(name="rom", contents=data)
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self.init_rom(name="rom", contents=data)
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def add_wb_master(self, wbm):
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self.bus.add_master(master=wbm)
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def add_wb_slave(self, address, interface, size=None):
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wb_name = None
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for name, region in self.bus.regions.items():
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if address == region.origin:
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wb_name = name
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break
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if wb_name is None:
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self.wb_slaves[address] = interface
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else:
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self.bus.add_slave(name=wb_name, slave=interface)
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def add_memory_region(self, name, origin, length, type="cached"):
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def add_memory_region(self, name, origin, length, type="cached"):
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self.bus.add_region(name, SoCRegion(origin=origin, size=length,
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self.bus.add_region(name, SoCRegion(origin=origin, size=length,
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cached="cached" in type,
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cached="cached" in type,
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linker="linker" in type))
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linker="linker" in type)
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)
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def register_mem(self, name, address, interface, size=0x10000000):
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self.bus.add_slave(name, interface, SoCRegion(origin=address, size=size))
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def register_rom(self, interface, rom_size=0xa000):
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self.bus.add_slave("rom", interface, SoCRegion(origin=self.cpu.reset_address, size=rom_size))
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def add_csr_region(self, name, origin, busword, obj):
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def add_csr_region(self, name, origin, busword, obj):
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self.csr_regions[name] = SoCCSRRegion(origin, busword, obj)
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self.csr_regions[name] = SoCCSRRegion(origin, busword, obj)
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# Finalization ---------------------------------------------------------------------------------
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def do_finalize(self):
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def do_finalize(self):
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# Retro-compatibility
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SoCCoreCompat.do_finalize(self)
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for address, interface in self.wb_slaves.items():
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wb_name = None
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for name, region in self.bus.regions.items():
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if address == region.origin:
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wb_name = name
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break
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self.bus.add_slave(name=wb_name, slave=interface)
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SoC.do_finalize(self)
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# Retro-compatibility
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for region in self.bus.regions.values():
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region.length = region.size
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region.type = "cached" if region.cached else "io"
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if region.linker:
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region.type += "+linker"
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self.csr_regions = self.csr.regions
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for name, value in self.config.items():
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self.add_config(name, value)
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# SoCCore arguments --------------------------------------------------------------------------------
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# SoCCore arguments --------------------------------------------------------------------------------
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