set LM32 reset address

misoclib/gensoc/__init__.py

@@ -39,7 +39,7 @@ class GenSoC(Module):
 		self._rom_registered = False
 
 		# Wishbone
-		self.submodules.cpu = lm32.LM32() # TODO: cpu_reset_address
+		self.submodules.cpu = lm32.LM32(cpu_reset_address)
 		self.submodules.sram = wishbone.SRAM(sram_size)
 		self.submodules.wishbone2csr = wishbone2csr.WB2CSR()
 
@@ -65,8 +65,7 @@ class GenSoC(Module):
 			"lm32_load_store_unit.v", "lm32_adder.v", "lm32_addsub.v", "lm32_logic_op.v",
 			"lm32_shifter.v", "lm32_multiplier.v", "lm32_mc_arithmetic.v",
 			"lm32_interrupt.v", "lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v",
-			"lm32_dcache.v", "lm32_top.v", "lm32_debug.v", "lm32_jtag.v", "jtag_cores.v",
-			"jtag_tap_spartan6.v", "lm32_itlb.v", "lm32_dtlb.v")
+			"lm32_dcache.v", "lm32_debug.v", "lm32_itlb.v", "lm32_dtlb.v")
 		platform.add_sources(os.path.join("verilog", "lm32"), "lm32_config.v")
 
 	def register_rom(self, rom_wb_if, bios_size=0x8000):

misoclib/lm32/__init__.py

@@ -2,50 +2,48 @@ from migen.fhdl.std import *
 from migen.bus import wishbone
 
 class LM32(Module):
-	def __init__(self):
+	def __init__(self, eba_reset):
 		self.ibus = i = wishbone.Interface()
 		self.dbus = d = wishbone.Interface()
 		self.interrupt = Signal(32)
-		self.ext_break = Signal()
 
 		###
 
 		i_adr_o = Signal(32)
 		d_adr_o = Signal(32)
-		self.specials += Instance("lm32_top",
-			Instance.Input("clk_i", ClockSignal()),
-			Instance.Input("rst_i", ResetSignal()),
+		self.specials += Instance("lm32_cpu",
+			p_eba_reset=Instance.PreformattedParam("32'h{:08x}".format(eba_reset)),
 
-			Instance.Input("interrupt", self.interrupt),
-			#Instance.Input("ext_break", self.ext_break),
+			i_clk_i=ClockSignal(),
+			i_rst_i=ResetSignal(),
 			
-			Instance.Output("I_ADR_O", i_adr_o),
-			Instance.Output("I_DAT_O", i.dat_w),
-			Instance.Output("I_SEL_O", i.sel),
-			Instance.Output("I_CYC_O", i.cyc),
-			Instance.Output("I_STB_O", i.stb),
-			Instance.Output("I_WE_O", i.we),
-			Instance.Output("I_CTI_O", i.cti),
-			Instance.Output("I_LOCK_O"),
-			Instance.Output("I_BTE_O", i.bte),
-			Instance.Input("I_DAT_I", i.dat_r),
-			Instance.Input("I_ACK_I", i.ack),
-			Instance.Input("I_ERR_I", i.err),
-			Instance.Input("I_RTY_I", 0),
+			i_interrupt=self.interrupt,
 		
-			Instance.Output("D_ADR_O", d_adr_o),
-			Instance.Output("D_DAT_O", d.dat_w),
-			Instance.Output("D_SEL_O", d.sel),
-			Instance.Output("D_CYC_O", d.cyc),
-			Instance.Output("D_STB_O", d.stb),
-			Instance.Output("D_WE_O", d.we),
-			Instance.Output("D_CTI_O", d.cti),
-			Instance.Output("D_LOCK_O"),
-			Instance.Output("D_BTE_O", d.bte),
-			Instance.Input("D_DAT_I", d.dat_r),
-			Instance.Input("D_ACK_I", d.ack),
-			Instance.Input("D_ERR_I", d.err),
-			Instance.Input("D_RTY_I", 0))
+			o_I_ADR_O=i_adr_o,
+			o_I_DAT_O=i.dat_w,
+			o_I_SEL_O=i.sel,
+			o_I_CYC_O=i.cyc,
+			o_I_STB_O=i.stb,
+			o_I_WE_O=i.we,
+			o_I_CTI_O=i.cti,
+			o_I_BTE_O=i.bte,
+			i_I_DAT_I=i.dat_r,
+			i_I_ACK_I=i.ack,
+			i_I_ERR_I=i.err,
+			i_I_RTY_I=0,
+			
+			o_D_ADR_O=d_adr_o,
+			o_D_DAT_O=d.dat_w,
+			o_D_SEL_O=d.sel,
+			o_D_CYC_O=d.cyc,
+			o_D_STB_O=d.stb,
+			o_D_WE_O=d.we,
+			o_D_CTI_O=d.cti,
+			o_D_BTE_O=d.bte,
+			i_D_DAT_I=d.dat_r,
+			i_D_ACK_I=d.ack,
+			i_D_ERR_I=d.err,
+			i_D_RTY_I=0)
 
 		self.comb += [
 			self.ibus.adr.eq(i_adr_o[2:]),

verilog/lm32/lm32_config.v

@@ -7,7 +7,7 @@
 //
 
 // Base address for exception vectors
-`define CFG_EBA_RESET 32'h00180000
+`define CFG_EBA_RESET 32'h00000000
 
 // Base address for the debug exception vectors. If the DC_RE flag is
 // set or the at_debug signal is asserted (see CFG_ALTERNATE_EBA) this

verilog/lm32/submodule

@@ -1 +1 @@
-Subproject commit 90651f0dcb02565bd69c634f4a811e94671d21ef
+Subproject commit 584924363b77ecdfcc364697f954400f8649c9e6