cpu/vexriscv_smp: Fix pbus data-width (Max of icache/dcache-width).

Fix boot with > 1 CPU or with FPU when using --with-wishbone-memory.

litex/soc/cores/cpu/vexriscv_smp/core.py

@@ -282,7 +282,7 @@ class VexRiscvSMP(CPU):
         self.jtag_tdo         = Signal()
         self.jtag_tdi         = Signal()
         self.interrupt        = Signal(32)
-        self.pbus             = pbus    = wishbone.Interface()
+        self.pbus             = pbus = wishbone.Interface(data_width=max(VexRiscvSMP.icache_width, VexRiscvSMP.dcache_width))
 
         self.periph_buses     = [pbus] # Peripheral buses (Connected to main SoC's bus).
         self.memory_buses     = []     # Memory buses (Connected directly to LiteDRAM).