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adding JTAG support for the xcau, Xilinx Artix UltraScale+

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This commit is contained in:
Andrew E Wilson 2022-06-07 00:45:27 -06:00
parent 50613f74c0
commit 9691d205b7
1 changed files with 1 additions and 1 deletions
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2
litex/soc/cores/jtag.py
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@ -307,7 +307,7 @@ class XilinxJTAG(Module):
prim_dict = {
# Primitive Name Ðevice (startswith)
"BSCAN_SPARTAN6" : ["xc6"],
"BSCANE2" : ["xc7a", "xc7k", "xc7v", "xc7z"] + ["xcku", "xcvu", "xczu"],
"BSCANE2" : ["xc7a", "xc7k", "xc7v", "xc7z"] + ["xcau", "xcku", "xcvu", "xczu"],
}
for prim, prim_devs in prim_dict.items():
for prim_dev in prim_devs: