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Revert "framebuffer: reset VTG"

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This reverts commit 6cb18f5ce3.

Conflicts:
	misoclib/framebuffer/__init__.py
	misoclib/framebuffer/format.py
This commit is contained in:
Sebastien Bourdeauducq 2013-11-19 23:48:00 +01:00
parent 2eabf97147
commit 96fcb3574e
2 changed files with 22 additions and 33 deletions
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2
misoclib/framebuffer/__init__.py
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@ -29,7 +29,6 @@ class Framebuffer(Module, AutoCSR):
self.comb += [ self.comb += [
self.fi.trigger.eq(self._enable.storage), self.fi.trigger.eq(self._enable.storage),
self.dma.generator.trigger.eq(self._enable.storage), self.dma.generator.trigger.eq(self._enable.storage),
vtg.enable.eq(self._enable.storage)
] ]
class Blender(PipelinedActor, AutoCSR): class Blender(PipelinedActor, AutoCSR):
@ -99,7 +98,6 @@ class MixFramebuffer(Module, AutoCSR):
setattr(self, "dma"+str(n), dma) setattr(self, "dma"+str(n), dma)
vtg = VTG(pack_factor) vtg = VTG(pack_factor)
self.comb += vtg.enable.eq(self._enable.storage)
g.add_connection(self.fi, vtg, sink_ep="timing") g.add_connection(self.fi, vtg, sink_ep="timing")
g.add_connection(self.blender, vtg, sink_ep="pixels") g.add_connection(self.blender, vtg, sink_ep="pixels")
g.add_connection(vtg, self.driver) g.add_connection(vtg, self.driver)

11
misoclib/framebuffer/format.py
View file

@ -49,7 +49,6 @@ class FrameInitiator(spi.SingleGenerator):
class VTG(Module): class VTG(Module):
def __init__(self, pack_factor): def __init__(self, pack_factor):
hbits_dyn = _hbits - log2_int(pack_factor) hbits_dyn = _hbits - log2_int(pack_factor)
self.enable = Signal()
self.timing = Sink([ self.timing = Sink([
("hres", hbits_dyn), ("hres", hbits_dyn),
("hsync_start", hbits_dyn), ("hsync_start", hbits_dyn),
@ -63,8 +62,6 @@ class VTG(Module):
self.phy = Source(phy_layout(pack_factor)) self.phy = Source(phy_layout(pack_factor))
self.busy = Signal() self.busy = Signal()
###
hactive = Signal() hactive = Signal()
vactive = Signal() vactive = Signal()
active = Signal() active = Signal()
@ -83,13 +80,12 @@ class VTG(Module):
), ),
generate_en.eq(self.timing.stb & (~active | self.pixels.stb)), generate_en.eq(self.timing.stb & (~active | self.pixels.stb)),
self.pixels.ack.eq(~self.enable | (self.phy.ack & active)), self.pixels.ack.eq(self.phy.ack & active),
self.phy.stb.eq(generate_en), self.phy.stb.eq(generate_en),
self.busy.eq(generate_en) self.busy.eq(generate_en)
] ]
tp = self.timing.payload tp = self.timing.payload
self.sync += [ self.sync += [
If(self.enable,
self.timing.ack.eq(0), self.timing.ack.eq(0),
If(generate_en & self.phy.ack, If(generate_en & self.phy.ack,
hcounter.eq(hcounter + 1), hcounter.eq(hcounter + 1),
@ -113,9 +109,4 @@ class VTG(Module):
If(vcounter == tp.vsync_start, self.phy.payload.vsync.eq(1)), If(vcounter == tp.vsync_start, self.phy.payload.vsync.eq(1)),
If(vcounter == tp.vsync_end, self.phy.payload.vsync.eq(0)) If(vcounter == tp.vsync_end, self.phy.payload.vsync.eq(0))
) )
).Else(
self.timing.ack.eq(1),
hcounter.eq(0),
vcounter.eq(0)
)
] ]