build/efinix/common: Switch to LiteXModule.
This commit is contained in:
Florent Kermarrec
parent
95e5e7302e
commit
9760493c32
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@ -41,7 +41,7 @@ def assert_is_signal_or_clocksignal(obj):
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# Efinix AsyncResetSynchronizer --------------------------------------------------------------------
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class EfinixAsyncResetSynchronizerImpl(Module):
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class EfinixAsyncResetSynchronizerImpl(LiteXModule):
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def __init__(self, cd, async_reset):
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rst1 = Signal()
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self.specials += [
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@ -71,7 +71,7 @@ class EfinixAsyncResetSynchronizer:
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# Efinix Clk Input ---------------------------------------------------------------------------------
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class EfinixClkInputImpl(Module):
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class EfinixClkInputImpl(LiteXModule):
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n = 0
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def __init__(self, i, o):
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platform = LiteXContext.platform
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@ -102,14 +102,14 @@ class EfinixClkInputImpl(Module):
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o = clk_out
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EfinixClkInputImpl.n += 1 # FIXME: Improve.
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class EfinixClkInput(Module):
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class EfinixClkInput(LiteXModule):
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@staticmethod
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def lower(dr):
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return EfinixClkInputImpl(dr.i, dr.o)
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# Efinix Clk Output --------------------------------------------------------------------------------
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class EfinixClkOutputImpl(Module):
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class EfinixClkOutputImpl(LiteXModule):
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def __init__(self, i, o):
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assert_is_signal_or_clocksignal(i)
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platform = LiteXContext.platform
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@ -124,14 +124,14 @@ class EfinixClkOutputImpl(Module):
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platform.toolchain.ifacewriter.blocks.append(block)
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platform.toolchain.excluded_ios.append(o)
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class EfinixClkOutput(Module):
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class EfinixClkOutput(LiteXModule):
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@staticmethod
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def lower(dr):
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return EfinixClkOutputImpl(dr.i, dr.o)
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# Efinix Tristate ----------------------------------------------------------------------------------
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class EfinixTristateImpl(Module):
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class EfinixTristateImpl(LiteXModule):
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def __init__(self, io, o, oe, i=None):
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platform = LiteXContext.platform
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if len(io) == 1:
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@ -162,14 +162,14 @@ class EfinixTristateImpl(Module):
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platform.toolchain.ifacewriter.blocks.append(block)
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platform.toolchain.excluded_ios.append(platform.get_pin(io))
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class EfinixTristate(Module):
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class EfinixTristate(LiteXModule):
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@staticmethod
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def lower(dr):
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return EfinixTristateImpl(dr.target, dr.o, dr.oe, dr.i)
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# Efinix DifferentialOutput ------------------------------------------------------------------------
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class EfinixDifferentialOutputImpl(Module):
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class EfinixDifferentialOutputImpl(LiteXModule):
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def __init__(self, i, o_p, o_n):
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platform = LiteXContext.platform
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# only keep _p
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@ -214,7 +214,7 @@ class EfinixDifferentialOutput:
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# Efinix DifferentialInput -------------------------------------------------------------------------
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class EfinixDifferentialInputImpl(Module):
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class EfinixDifferentialInputImpl(LiteXModule):
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def __init__(self, i_p, i_n, o):
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platform = LiteXContext.platform
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# only keep _p
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@ -274,7 +274,7 @@ class EfinixDifferentialInput:
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# Efinix DDRTristate -------------------------------------------------------------------------------
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class EfinixDDRTristateImpl(Module):
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class EfinixDDRTristateImpl(LiteXModule):
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def __init__(self, io, o1, o2, oe1, oe2, i1, i2, clk):
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assert oe1 == oe2
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assert_is_signal_or_clocksignal(clk)
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@ -319,7 +319,7 @@ class EfinixDDRTristate:
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# Efinix SDRTristate -------------------------------------------------------------------------------
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class EfinixSDRTristateImpl(Module):
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class EfinixSDRTristateImpl(LiteXModule):
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def __init__(self, io, o, oe, i, clk):
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assert_is_signal_or_clocksignal(clk)
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platform = LiteXContext.platform
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@ -353,14 +353,14 @@ class EfinixSDRTristateImpl(Module):
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platform.toolchain.excluded_ios.append(platform.get_pin(io))
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class EfinixSDRTristate(Module):
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class EfinixSDRTristate(LiteXModule):
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@staticmethod
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def lower(dr):
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return EfinixSDRTristateImpl(dr.io, dr.o, dr.oe, dr.i, dr.clk)
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# Efinix SDROutput ---------------------------------------------------------------------------------
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class EfinixSDROutputImpl(Module):
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class EfinixSDROutputImpl(LiteXModule):
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def __init__(self, i, o, clk):
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assert_is_signal_or_clocksignal(clk)
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platform = LiteXContext.platform
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@ -386,14 +386,14 @@ class EfinixSDROutputImpl(Module):
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platform.toolchain.excluded_ios.append(platform.get_pin(o))
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class EfinixSDROutput(Module):
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class EfinixSDROutput(LiteXModule):
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@staticmethod
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def lower(dr):
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return EfinixSDROutputImpl(dr.i, dr.o, dr.clk)
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# Efinix DDROutput ---------------------------------------------------------------------------------
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class EfinixDDROutputImpl(Module):
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class EfinixDDROutputImpl(LiteXModule):
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def __init__(self, i1, i2, o, clk):
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assert_is_signal_or_clocksignal(clk)
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platform = LiteXContext.platform
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@ -427,7 +427,7 @@ class EfinixDDROutput:
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# Efinix SDRInput ----------------------------------------------------------------------------------
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class EfinixSDRInputImpl(Module):
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class EfinixSDRInputImpl(LiteXModule):
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def __init__(self, i, o, clk):
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assert_is_signal_or_clocksignal(clk)
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platform = LiteXContext.platform
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@ -457,7 +457,7 @@ class EfinixSDRInput:
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# Efinix DDRInput ----------------------------------------------------------------------------------
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class EfinixDDRInputImpl(Module):
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class EfinixDDRInputImpl(LiteXModule):
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def __init__(self, i, o1, o2, clk):
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assert_is_signal_or_clocksignal(clk)
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platform = LiteXContext.platform
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