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build/efinix/common: Switch to LiteXModule.

This commit is contained in:
Florent Kermarrec 2024-09-26 17:46:07 +02:00
parent 95e5e7302e
commit 9760493c32
1 changed files with 17 additions and 17 deletions
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34
litex/build/efinix/common.py
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@ -41,7 +41,7 @@ def assert_is_signal_or_clocksignal(obj):
# Efinix AsyncResetSynchronizer -------------------------------------------------------------------- # Efinix AsyncResetSynchronizer --------------------------------------------------------------------
class EfinixAsyncResetSynchronizerImpl(Module): class EfinixAsyncResetSynchronizerImpl(LiteXModule):
def __init__(self, cd, async_reset): def __init__(self, cd, async_reset):
rst1 = Signal() rst1 = Signal()
self.specials += [ self.specials += [
@ -71,7 +71,7 @@ class EfinixAsyncResetSynchronizer:
# Efinix Clk Input --------------------------------------------------------------------------------- # Efinix Clk Input ---------------------------------------------------------------------------------
class EfinixClkInputImpl(Module): class EfinixClkInputImpl(LiteXModule):
n = 0 n = 0
def __init__(self, i, o): def __init__(self, i, o):
platform = LiteXContext.platform platform = LiteXContext.platform
@ -102,14 +102,14 @@ class EfinixClkInputImpl(Module):
o = clk_out o = clk_out
EfinixClkInputImpl.n += 1 # FIXME: Improve. EfinixClkInputImpl.n += 1 # FIXME: Improve.
class EfinixClkInput(Module): class EfinixClkInput(LiteXModule):
@staticmethod @staticmethod
def lower(dr): def lower(dr):
return EfinixClkInputImpl(dr.i, dr.o) return EfinixClkInputImpl(dr.i, dr.o)
# Efinix Clk Output -------------------------------------------------------------------------------- # Efinix Clk Output --------------------------------------------------------------------------------
class EfinixClkOutputImpl(Module): class EfinixClkOutputImpl(LiteXModule):
def __init__(self, i, o): def __init__(self, i, o):
assert_is_signal_or_clocksignal(i) assert_is_signal_or_clocksignal(i)
platform = LiteXContext.platform platform = LiteXContext.platform
@ -124,14 +124,14 @@ class EfinixClkOutputImpl(Module):
platform.toolchain.ifacewriter.blocks.append(block) platform.toolchain.ifacewriter.blocks.append(block)
platform.toolchain.excluded_ios.append(o) platform.toolchain.excluded_ios.append(o)
class EfinixClkOutput(Module): class EfinixClkOutput(LiteXModule):
@staticmethod @staticmethod
def lower(dr): def lower(dr):
return EfinixClkOutputImpl(dr.i, dr.o) return EfinixClkOutputImpl(dr.i, dr.o)
# Efinix Tristate ---------------------------------------------------------------------------------- # Efinix Tristate ----------------------------------------------------------------------------------
class EfinixTristateImpl(Module): class EfinixTristateImpl(LiteXModule):
def __init__(self, io, o, oe, i=None): def __init__(self, io, o, oe, i=None):
platform = LiteXContext.platform platform = LiteXContext.platform
if len(io) == 1: if len(io) == 1:
@ -162,14 +162,14 @@ class EfinixTristateImpl(Module):
platform.toolchain.ifacewriter.blocks.append(block) platform.toolchain.ifacewriter.blocks.append(block)
platform.toolchain.excluded_ios.append(platform.get_pin(io)) platform.toolchain.excluded_ios.append(platform.get_pin(io))
class EfinixTristate(Module): class EfinixTristate(LiteXModule):
@staticmethod @staticmethod
def lower(dr): def lower(dr):
return EfinixTristateImpl(dr.target, dr.o, dr.oe, dr.i) return EfinixTristateImpl(dr.target, dr.o, dr.oe, dr.i)
# Efinix DifferentialOutput ------------------------------------------------------------------------ # Efinix DifferentialOutput ------------------------------------------------------------------------
class EfinixDifferentialOutputImpl(Module): class EfinixDifferentialOutputImpl(LiteXModule):
def __init__(self, i, o_p, o_n): def __init__(self, i, o_p, o_n):
platform = LiteXContext.platform platform = LiteXContext.platform
# only keep _p # only keep _p
@ -214,7 +214,7 @@ class EfinixDifferentialOutput:
# Efinix DifferentialInput ------------------------------------------------------------------------- # Efinix DifferentialInput -------------------------------------------------------------------------
class EfinixDifferentialInputImpl(Module): class EfinixDifferentialInputImpl(LiteXModule):
def __init__(self, i_p, i_n, o): def __init__(self, i_p, i_n, o):
platform = LiteXContext.platform platform = LiteXContext.platform
# only keep _p # only keep _p
@ -274,7 +274,7 @@ class EfinixDifferentialInput:
# Efinix DDRTristate ------------------------------------------------------------------------------- # Efinix DDRTristate -------------------------------------------------------------------------------
class EfinixDDRTristateImpl(Module): class EfinixDDRTristateImpl(LiteXModule):
def __init__(self, io, o1, o2, oe1, oe2, i1, i2, clk): def __init__(self, io, o1, o2, oe1, oe2, i1, i2, clk):
assert oe1 == oe2 assert oe1 == oe2
assert_is_signal_or_clocksignal(clk) assert_is_signal_or_clocksignal(clk)
@ -319,7 +319,7 @@ class EfinixDDRTristate:
# Efinix SDRTristate ------------------------------------------------------------------------------- # Efinix SDRTristate -------------------------------------------------------------------------------
class EfinixSDRTristateImpl(Module): class EfinixSDRTristateImpl(LiteXModule):
def __init__(self, io, o, oe, i, clk): def __init__(self, io, o, oe, i, clk):
assert_is_signal_or_clocksignal(clk) assert_is_signal_or_clocksignal(clk)
platform = LiteXContext.platform platform = LiteXContext.platform
@ -353,14 +353,14 @@ class EfinixSDRTristateImpl(Module):
platform.toolchain.excluded_ios.append(platform.get_pin(io)) platform.toolchain.excluded_ios.append(platform.get_pin(io))
class EfinixSDRTristate(Module): class EfinixSDRTristate(LiteXModule):
@staticmethod @staticmethod
def lower(dr): def lower(dr):
return EfinixSDRTristateImpl(dr.io, dr.o, dr.oe, dr.i, dr.clk) return EfinixSDRTristateImpl(dr.io, dr.o, dr.oe, dr.i, dr.clk)
# Efinix SDROutput --------------------------------------------------------------------------------- # Efinix SDROutput ---------------------------------------------------------------------------------
class EfinixSDROutputImpl(Module): class EfinixSDROutputImpl(LiteXModule):
def __init__(self, i, o, clk): def __init__(self, i, o, clk):
assert_is_signal_or_clocksignal(clk) assert_is_signal_or_clocksignal(clk)
platform = LiteXContext.platform platform = LiteXContext.platform
@ -386,14 +386,14 @@ class EfinixSDROutputImpl(Module):
platform.toolchain.excluded_ios.append(platform.get_pin(o)) platform.toolchain.excluded_ios.append(platform.get_pin(o))
class EfinixSDROutput(Module): class EfinixSDROutput(LiteXModule):
@staticmethod @staticmethod
def lower(dr): def lower(dr):
return EfinixSDROutputImpl(dr.i, dr.o, dr.clk) return EfinixSDROutputImpl(dr.i, dr.o, dr.clk)
# Efinix DDROutput --------------------------------------------------------------------------------- # Efinix DDROutput ---------------------------------------------------------------------------------
class EfinixDDROutputImpl(Module): class EfinixDDROutputImpl(LiteXModule):
def __init__(self, i1, i2, o, clk): def __init__(self, i1, i2, o, clk):
assert_is_signal_or_clocksignal(clk) assert_is_signal_or_clocksignal(clk)
platform = LiteXContext.platform platform = LiteXContext.platform
@ -427,7 +427,7 @@ class EfinixDDROutput:
# Efinix SDRInput ---------------------------------------------------------------------------------- # Efinix SDRInput ----------------------------------------------------------------------------------
class EfinixSDRInputImpl(Module): class EfinixSDRInputImpl(LiteXModule):
def __init__(self, i, o, clk): def __init__(self, i, o, clk):
assert_is_signal_or_clocksignal(clk) assert_is_signal_or_clocksignal(clk)
platform = LiteXContext.platform platform = LiteXContext.platform
@ -457,7 +457,7 @@ class EfinixSDRInput:
# Efinix DDRInput ---------------------------------------------------------------------------------- # Efinix DDRInput ----------------------------------------------------------------------------------
class EfinixDDRInputImpl(Module): class EfinixDDRInputImpl(LiteXModule):
def __init__(self, i, o1, o2, clk): def __init__(self, i, o1, o2, clk):
assert_is_signal_or_clocksignal(clk) assert_is_signal_or_clocksignal(clk)
platform = LiteXContext.platform platform = LiteXContext.platform