soc: remove ns function

misoclib/soc/__init__.py

@@ -1,6 +1,5 @@
 import os, struct
 from operator import itemgetter
-from math import ceil
 
 from migen.fhdl.std import *
 from migen.bank import csrgen
@@ -188,9 +187,3 @@ class SoC(Module):
 			for k, v in sorted(self.interrupt_map.items(), key=itemgetter(1)):
 				if hasattr(self, k):
 					self.comb += self.cpu_or_bridge.interrupt[v].eq(getattr(self, k).ev.irq)
-
-	def ns(self, t, margin=True):
-		clk_period_ns = 1000000000/self.clk_freq
-		if margin:
-			t += clk_period_ns/2
-		return ceil(t/clk_period_ns)

targets/mlabs_video.py

@@ -1,5 +1,6 @@
 import os
 from fractions import Fraction
+from math import ceil
 
 from migen.fhdl.std import *
 from mibuild.generic_platform import ConstraintError
@@ -47,21 +48,18 @@ class BaseSoC(SDRAMSoC):
 			self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"), MT46V32M16(self.clk_freq),
 				rd_bitslip=0, wr_bitslip=3, dqs_ddr_alignment="C1")
 			self.register_sdram_phy(self.ddrphy)
-
 			self.comb += [
 				self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
 				self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb)
 			]
 
-		self.submodules.norflash = norflash16.NorFlash16(platform.request("norflash"),
-			self.ns(110), self.ns(50))
-		self.flash_boot_address = 0x001a0000
-
-		# If not in ROM, BIOS is in // NOR flash
 		if not self.with_integrated_rom:
+			clk_period_ns = 1000000000/self.clk_freq
+			self.submodules.norflash = norflash16.NorFlash16(platform.request("norflash"),
+				ceil(110/clk_period_ns), ceil(50/clk_period_ns))
+			self.flash_boot_address = 0x001a0000
 			self.register_rom(self.norflash.bus)
 
-
 		platform.add_platform_command("""
 INST "mxcrg/wr_bufpll" LOC = "BUFPLL_X0Y2";
 INST "mxcrg/rd_bufpll" LOC = "BUFPLL_X0Y3";