platforms/targets: fix CI.
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22bcbec03a
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98d1b45157
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@ -199,5 +199,5 @@ class Platform(XilinxPlatform):
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def do_finalize(self, fragment):
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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XilinxPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
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self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
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self.add_period_constraint(self.lookup_request("eth_clocks", loose=True), 1e9/50e6)
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self.add_period_constraint(self.lookup_request("eth_clocks:ref_clk", loose=True), 1e9/50e6)
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@ -243,5 +243,5 @@ class Platform(XilinxPlatform):
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def do_finalize(self, fragment):
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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XilinxPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
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self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
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self.add_period_constraint(self.lookup_request("eth_clocks", loose=True), 1e9/125e6)
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self.add_period_constraint(self.lookup_request("eth_clocks:rx", loose=True), 1e9/125e6)
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@ -134,7 +134,6 @@ class TestTargets(unittest.TestCase):
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litex/boards/targets/simple.py litex.boards.platforms.{p} \
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litex/boards/targets/simple.py litex.boards.platforms.{p} \
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--cpu-type=vexriscv \
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--cpu-type=vexriscv \
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--no-compile-software \
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--no-compile-software \
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--no-compile-gateware \
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--uart-name=stub \
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--uart-name=stub \
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""".format(p=p)
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""".format(p=p)
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subprocess.check_call(cmd, shell=True)
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subprocess.check_call(cmd, shell=True)
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@ -155,7 +154,6 @@ litex/boards/targets/simple.py litex.boards.platforms.arty \
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--cpu-type={c} \
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--cpu-type={c} \
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--cpu-variant={v} \
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--cpu-variant={v} \
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--no-compile-software \
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--no-compile-software \
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--no-compile-gateware \
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--uart-name=stub \
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--uart-name=stub \
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""".format(c=cpu, v=variant)
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""".format(c=cpu, v=variant)
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subprocess.check_output(cmd, shell=True)
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subprocess.check_output(cmd, shell=True)
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