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mibuild/xilinx/common: add XilinxDDROutput

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This commit is contained in:
Florent Kermarrec 2015-03-16 22:53:05 +01:00
parent 69ce6dd48c
commit 993059a59c
1 changed files with 14 additions and 0 deletions
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14
mibuild/xilinx/common.py
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@ -84,10 +84,24 @@ class XilinxDifferentialOutput:
def lower(dr): def lower(dr):
return XilinxDifferentialOutputImpl(dr.i, dr.o_p, dr.o_n) return XilinxDifferentialOutputImpl(dr.i, dr.o_p, dr.o_n)
class XilinxDDROutputImpl(Module):
def __init__(self, i1, i2, o, clk):
self.specials += Instance("ODDR",
p_DDR_CLK_EDGE="SAME_EDGE",
i_C=clk, i_CE=1, i_S=0, i_R=0,
i_D1=i1, i_D2=i2, o_Q=o,
)
class XilinxDDROutput:
@staticmethod
def lower(dr):
return XilinxDDROutputImpl(dr.i1, dr.i2, dr.o, dr.clk)
xilinx_special_overrides = { xilinx_special_overrides = {
NoRetiming: XilinxNoRetiming, NoRetiming: XilinxNoRetiming,
MultiReg: XilinxMultiReg, MultiReg: XilinxMultiReg,
AsyncResetSynchronizer: XilinxAsyncResetSynchronizer, AsyncResetSynchronizer: XilinxAsyncResetSynchronizer,
DifferentialInput: XilinxDifferentialInput, DifferentialInput: XilinxDifferentialInput,
DifferentialOutput: XilinxDifferentialOutput, DifferentialOutput: XilinxDifferentialOutput,
DDROutput: XilinxDDROutput
} }