code clean up
This commit is contained in:
Florent Kermarrec
parent
a8300a2e93
commit
996a56c335
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@ -28,11 +28,9 @@ class LiteEthARPPacketizer(LiteEthPacketizer):
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class LiteEthARPTX(Module):
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def __init__(self, mac_address, ip_address):
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self.sink = sink = Sink(_arp_table_layout)
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self.source = Source(eth_mac_description(8))
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self.source = source = Source(eth_mac_description(8))
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###
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packetizer = LiteEthARPPacketizer()
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self.submodules += packetizer
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source = packetizer.sink
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self.submodules.packetizer = packetizer = LiteEthARPPacketizer()
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counter = Counter(max=max(arp_header_len, eth_min_len))
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self.submodules += counter
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@ -47,34 +45,35 @@ class LiteEthARPTX(Module):
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)
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)
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self.comb += [
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source.sop.eq(counter.value == 0),
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source.eop.eq(counter.value == max(arp_header_len, eth_min_len)-1),
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source.hwtype.eq(arp_hwtype_ethernet),
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source.proto.eq(arp_proto_ip),
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source.hwsize.eq(6),
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source.protosize.eq(4),
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source.sender_mac.eq(mac_address),
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source.sender_ip.eq(ip_address),
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packetizer.sink.sop.eq(counter.value == 0),
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packetizer.sink.eop.eq(counter.value == max(arp_header_len, eth_min_len)-1),
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packetizer.sink.hwtype.eq(arp_hwtype_ethernet),
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packetizer.sink.proto.eq(arp_proto_ip),
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packetizer.sink.hwsize.eq(6),
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packetizer.sink.protosize.eq(4),
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packetizer.sink.sender_mac.eq(mac_address),
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packetizer.sink.sender_ip.eq(ip_address),
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If(sink.reply,
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source.opcode.eq(arp_opcode_reply),
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source.target_mac.eq(sink.mac_address),
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source.target_ip.eq(sink.ip_address)
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packetizer.sink.opcode.eq(arp_opcode_reply),
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packetizer.sink.target_mac.eq(sink.mac_address),
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packetizer.sink.target_ip.eq(sink.ip_address)
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).Elif(sink.request,
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source.opcode.eq(arp_opcode_request),
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source.target_mac.eq(0xffffffffffff),
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source.target_ip.eq(sink.ip_address)
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packetizer.sink.opcode.eq(arp_opcode_request),
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packetizer.sink.target_mac.eq(0xffffffffffff),
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packetizer.sink.target_ip.eq(sink.ip_address)
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)
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]
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fsm.act("SEND",
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source.stb.eq(1),
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Record.connect(packetizer.source, self.source),
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self.source.target_mac.eq(source.target_mac),
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self.source.sender_mac.eq(mac_address),
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self.source.ethernet_type.eq(ethernet_type_arp),
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If(self.source.stb & self.source.ack,
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sink.ack.eq(source.eop),
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packetizer.sink.stb.eq(1),
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Record.connect(packetizer.source, source),
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source.target_mac.eq(packetizer.sink.target_mac),
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source.sender_mac.eq(mac_address),
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source.ethernet_type.eq(ethernet_type_arp),
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If(source.stb & source.ack,
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counter.ce.eq(1),
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If(self.source.eop,
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If(source.eop,
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sink.ack.eq(1),
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NextState("IDLE")
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)
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)
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@ -82,41 +81,39 @@ class LiteEthARPTX(Module):
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class LiteEthARPRX(Module):
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def __init__(self, mac_address, ip_address):
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self.sink = Sink(eth_mac_description(8))
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self.sink = sink = Sink(eth_mac_description(8))
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self.source = source = Source(_arp_table_layout)
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###
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depacketizer = LiteEthARPDepacketizer()
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self.submodules += depacketizer
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self.comb += Record.connect(self.sink, depacketizer.sink)
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sink = depacketizer.source
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self.submodules.depacketizer = depacketizer = LiteEthARPDepacketizer()
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self.comb += Record.connect(sink, depacketizer.sink)
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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sink.ack.eq(1),
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If(sink.stb & sink.sop,
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sink.ack.eq(0),
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depacketizer.source.ack.eq(1),
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If(depacketizer.source.stb & depacketizer.source.sop,
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depacketizer.source.ack.eq(0),
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NextState("CHECK")
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)
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)
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valid = Signal()
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self.comb += valid.eq(
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sink.stb &
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(sink.hwtype == arp_hwtype_ethernet) &
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(sink.proto == arp_proto_ip) &
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(sink.hwsize == 6) &
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(sink.protosize == 4) &
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(sink.target_ip == ip_address)
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depacketizer.source.stb &
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(depacketizer.source.hwtype == arp_hwtype_ethernet) &
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(depacketizer.source.proto == arp_proto_ip) &
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(depacketizer.source.hwsize == 6) &
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(depacketizer.source.protosize == 4) &
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(depacketizer.source.target_ip == ip_address)
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)
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reply = Signal()
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request = Signal()
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self.comb += Case(sink.opcode, {
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self.comb += Case(depacketizer.source.opcode, {
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arp_opcode_request : [request.eq(1)],
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arp_opcode_reply : [reply.eq(1)],
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"default" : []
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})
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self.comb += [
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source.ip_address.eq(sink.sender_ip),
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source.mac_address.eq(sink.sender_mac)
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source.ip_address.eq(depacketizer.source.sender_ip),
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source.mac_address.eq(depacketizer.source.sender_mac)
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]
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fsm.act("CHECK",
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If(valid,
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@ -127,8 +124,8 @@ class LiteEthARPRX(Module):
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NextState("TERMINATE")
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),
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fsm.act("TERMINATE",
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sink.ack.eq(1),
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If(sink.stb & sink.eop,
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depacketizer.source.ack.eq(1),
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If(depacketizer.source.stb & depacketizer.source.eop,
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NextState("IDLE")
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)
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)
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@ -153,8 +150,8 @@ class LiteEthARPTable(Module):
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request_ip_address.d.eq(request.ip_address)
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]
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# Note: Only store 1 IP/MAC couple, can be improved with a real
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# table in the future to improve performance when packet are
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# Note: Store only 1 IP/MAC couple, can be improved with a real
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# table in the future to improve performance when packets are
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# targeting multiple destinations.
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update = Signal()
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cached_valid = Signal()
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@ -166,7 +163,7 @@ class LiteEthARPTable(Module):
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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# Note: for simplicicy, if APR table is busy response from arp_rx
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# is lost. This is compensated by the protocol (retry)
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# is lost. This is compensated by the protocol (retries)
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If(sink.stb & sink.request,
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NextState("SEND_REPLY")
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).Elif(sink.stb & sink.reply & request_pending.q,
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@ -251,15 +248,15 @@ class LiteEthARPTable(Module):
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class LiteEthARP(Module):
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def __init__(self, mac, mac_address, ip_address, clk_freq):
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self.submodules.tx = LiteEthARPTX(mac_address, ip_address)
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self.submodules.rx = LiteEthARPRX(mac_address, ip_address)
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self.submodules.table = LiteEthARPTable(clk_freq)
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self.submodules.tx = tx = LiteEthARPTX(mac_address, ip_address)
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self.submodules.rx = rx = LiteEthARPRX(mac_address, ip_address)
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self.submodules.table = table = LiteEthARPTable(clk_freq)
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self.comb += [
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Record.connect(self.rx.source, self.table.sink),
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Record.connect(self.table.source, self.tx.sink)
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Record.connect(rx.source, table.sink),
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Record.connect(table.source, tx.sink)
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]
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mac_port = mac.crossbar.get_port(ethernet_type_arp)
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self.comb += [
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Record.connect(self.tx.source, mac_port.sink),
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Record.connect(mac_port.source, self.rx.sink)
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Record.connect(tx.source, mac_port.sink),
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Record.connect(mac_port.source, rx.sink)
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]
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@ -20,64 +20,60 @@ class LiteEthICMPPacketizer(LiteEthPacketizer):
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class LiteEthICMPTX(Module):
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def __init__(self, ip_address):
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self.sink = Sink(eth_icmp_user_description(8))
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self.source = Source(eth_ipv4_user_description(8))
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self.sink = sink = Sink(eth_icmp_user_description(8))
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self.source = source = Source(eth_ipv4_user_description(8))
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###
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packetizer = LiteEthICMPPacketizer()
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self.submodules += packetizer
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self.submodules.packetizer = packetizer = LiteEthICMPPacketizer()
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self.comb += [
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packetizer.sink.stb.eq(self.sink.stb),
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packetizer.sink.sop.eq(self.sink.sop),
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packetizer.sink.eop.eq(self.sink.eop),
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self.sink.ack.eq(packetizer.sink.ack),
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packetizer.sink.msgtype.eq(self.sink.msgtype),
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packetizer.sink.code.eq(self.sink.code),
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packetizer.sink.checksum.eq(self.sink.checksum),
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packetizer.sink.quench.eq(self.sink.quench),
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packetizer.sink.data.eq(self.sink.data)
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packetizer.sink.stb.eq(sink.stb),
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packetizer.sink.sop.eq(sink.sop),
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packetizer.sink.eop.eq(sink.eop),
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sink.ack.eq(packetizer.sink.ack),
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packetizer.sink.msgtype.eq(sink.msgtype),
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packetizer.sink.code.eq(sink.code),
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packetizer.sink.checksum.eq(sink.checksum),
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packetizer.sink.quench.eq(sink.quench),
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packetizer.sink.data.eq(sink.data)
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]
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sink = packetizer.source
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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sink.ack.eq(1),
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If(sink.stb & sink.sop,
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sink.ack.eq(0),
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packetizer.source.ack.eq(1),
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If(packetizer.source.stb & packetizer.source.sop,
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packetizer.source.ack.eq(0),
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NextState("SEND")
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)
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)
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fsm.act("SEND",
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Record.connect(packetizer.source, self.source),
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self.source.length.eq(self.sink.length + icmp_header_len),
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self.source.protocol.eq(icmp_protocol),
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self.source.ip_address.eq(self.sink.ip_address),
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If(self.source.stb & self.source.eop & self.source.ack,
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Record.connect(packetizer.source, source),
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source.length.eq(sink.length + icmp_header_len),
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source.protocol.eq(icmp_protocol),
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source.ip_address.eq(sink.ip_address),
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If(source.stb & source.eop & source.ack,
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NextState("IDLE")
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)
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)
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class LiteEthICMPRX(Module):
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def __init__(self, ip_address):
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self.sink = Sink(eth_ipv4_user_description(8))
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self.sink = sink = Sink(eth_ipv4_user_description(8))
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self.source = source = Source(eth_icmp_user_description(8))
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###
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depacketizer = LiteEthICMPDepacketizer()
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self.submodules += depacketizer
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self.comb += Record.connect(self.sink, depacketizer.sink)
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sink = depacketizer.source
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self.submodules.depacketizer = depacketizer = LiteEthICMPDepacketizer()
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self.comb += Record.connect(sink, depacketizer.sink)
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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sink.ack.eq(1),
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If(sink.stb & sink.sop,
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sink.ack.eq(0),
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depacketizer.source.ack.eq(1),
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If(depacketizer.source.stb & depacketizer.source.sop,
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depacketizer.source.ack.eq(0),
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NextState("CHECK")
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)
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)
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valid = Signal()
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self.comb += valid.eq(
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sink.stb &
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(self.sink.protocol == icmp_protocol)
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depacketizer.source.stb &
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(sink.protocol == icmp_protocol)
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)
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fsm.act("CHECK",
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If(valid,
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@ -87,55 +83,55 @@ class LiteEthICMPRX(Module):
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)
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)
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self.comb += [
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source.sop.eq(sink.sop),
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source.eop.eq(sink.eop),
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source.msgtype.eq(sink.msgtype),
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source.code.eq(sink.code),
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source.checksum.eq(sink.checksum),
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source.quench.eq(sink.quench),
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source.ip_address.eq(self.sink.ip_address),
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source.length.eq(self.sink.length - icmp_header_len),
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source.data.eq(sink.data),
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source.error.eq(sink.error)
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source.sop.eq(depacketizer.source.sop),
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source.eop.eq(depacketizer.source.eop),
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source.msgtype.eq(depacketizer.source.msgtype),
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source.code.eq(depacketizer.source.code),
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source.checksum.eq(depacketizer.source.checksum),
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source.quench.eq(depacketizer.source.quench),
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source.ip_address.eq(sink.ip_address),
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source.length.eq(sink.length - icmp_header_len),
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source.data.eq(depacketizer.source.data),
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source.error.eq(depacketizer.source.error)
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]
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fsm.act("PRESENT",
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source.stb.eq(sink.stb),
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sink.ack.eq(source.ack),
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source.stb.eq(depacketizer.source.stb),
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depacketizer.source.ack.eq(source.ack),
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If(source.stb & source.eop & source.ack,
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NextState("IDLE")
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)
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)
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fsm.act("DROP",
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sink.ack.eq(1),
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If(sink.stb & sink.eop & sink.ack,
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depacketizer.source.ack.eq(1),
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If(depacketizer.source.stb & depacketizer.source.eop & depacketizer.source.ack,
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NextState("IDLE")
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)
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)
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class LiteEthICMPEcho(Module):
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def __init__(self):
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self.sink = Sink(eth_icmp_user_description(8))
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self.source = Source(eth_icmp_user_description(8))
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self.sink = sink = Sink(eth_icmp_user_description(8))
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self.source = source = Source(eth_icmp_user_description(8))
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###
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self.submodules.fifo = SyncFIFO(eth_icmp_user_description(8), 512, buffered=True)
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self.submodules.fifo = fifo = SyncFIFO(eth_icmp_user_description(8), 512, buffered=True)
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self.comb += [
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Record.connect(self.sink, self.fifo.sink),
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Record.connect(self.fifo.source, self.source),
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Record.connect(sink, fifo.sink),
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Record.connect(fifo.source, source),
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self.source.msgtype.eq(0x0),
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self.source.checksum.eq(~((~self.fifo.source.checksum)-0x0800))
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self.source.checksum.eq(~((~fifo.source.checksum)-0x0800))
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]
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class LiteEthICMP(Module):
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def __init__(self, ip, ip_address):
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self.submodules.tx = LiteEthICMPTX(ip_address)
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self.submodules.rx = LiteEthICMPRX(ip_address)
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self.submodules.echo = LiteEthICMPEcho()
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self.submodules.tx = tx = LiteEthICMPTX(ip_address)
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self.submodules.rx = rx = LiteEthICMPRX(ip_address)
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self.submodules.echo = echo = LiteEthICMPEcho()
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self.comb += [
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Record.connect(self.rx.source, self.echo.sink),
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Record.connect(self.echo.source, self.tx.sink)
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Record.connect(rx.source, echo.sink),
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Record.connect(echo.source, tx.sink)
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]
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ip_port = ip.crossbar.get_port(icmp_protocol)
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self.comb += [
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Record.connect(self.tx.source, ip_port.sink),
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Record.connect(ip_port.source, self.rx.sink)
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Record.connect(tx.source, ip_port.sink),
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Record.connect(ip_port.source, rx.sink)
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]
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@ -20,14 +20,14 @@ class LiteEthIPV4Packetizer(LiteEthPacketizer):
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ipv4_header_len)
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class LiteEthIPV4Checksum(Module):
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def __init__(self, skip_header=False):
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def __init__(self, skip_checksum=False):
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self.header = Signal(ipv4_header_len*8)
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self.value = Signal(16)
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###
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s = Signal(17)
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r = Signal(17)
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for i in range(ipv4_header_len//2):
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if skip_header and i == 5:
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if skip_checksum and (i == ipv4_header["checksum"].byte//2):
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pass
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else:
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s_next = Signal(17)
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@ -41,31 +41,28 @@ class LiteEthIPV4Checksum(Module):
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class LiteEthIPTX(Module):
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def __init__(self, mac_address, ip_address, arp_table):
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self.sink = Sink(eth_ipv4_user_description(8))
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self.source = Source(eth_mac_description(8))
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self.sink = sink = Sink(eth_ipv4_user_description(8))
|
||||
self.source = source = Source(eth_mac_description(8))
|
||||
self.target_unreachable = Signal()
|
||||
###
|
||||
packetizer = LiteEthIPV4Packetizer()
|
||||
self.submodules += packetizer
|
||||
self.submodules.packetizer = packetizer = LiteEthIPV4Packetizer()
|
||||
self.comb += [
|
||||
packetizer.sink.stb.eq(self.sink.stb),
|
||||
packetizer.sink.sop.eq(self.sink.sop),
|
||||
packetizer.sink.eop.eq(self.sink.eop),
|
||||
self.sink.ack.eq(packetizer.sink.ack),
|
||||
packetizer.sink.target_ip.eq(self.sink.ip_address),
|
||||
packetizer.sink.protocol.eq(self.sink.protocol),
|
||||
packetizer.sink.total_length.eq(self.sink.length + (0x5*4)),
|
||||
packetizer.sink.stb.eq(sink.stb),
|
||||
packetizer.sink.sop.eq(sink.sop),
|
||||
packetizer.sink.eop.eq(sink.eop),
|
||||
sink.ack.eq(packetizer.sink.ack),
|
||||
packetizer.sink.target_ip.eq(sink.ip_address),
|
||||
packetizer.sink.protocol.eq(sink.protocol),
|
||||
packetizer.sink.total_length.eq(sink.length + (0x5*4)),
|
||||
packetizer.sink.version.eq(0x4), # ipv4
|
||||
packetizer.sink.ihl.eq(0x5), # 20 bytes
|
||||
packetizer.sink.identification.eq(0),
|
||||
packetizer.sink.ttl.eq(0x80),
|
||||
packetizer.sink.sender_ip.eq(ip_address),
|
||||
packetizer.sink.data.eq(self.sink.data)
|
||||
packetizer.sink.data.eq(sink.data)
|
||||
]
|
||||
sink = packetizer.source
|
||||
|
||||
checksum = LiteEthIPV4Checksum(skip_header=True)
|
||||
self.submodules += checksum
|
||||
self.submodules.checksum = checksum = LiteEthIPV4Checksum(skip_checksum=True)
|
||||
self.comb += [
|
||||
checksum.header.eq(packetizer.header),
|
||||
packetizer.sink.checksum.eq(checksum.value)
|
||||
|
|
@ -75,13 +72,13 @@ class LiteEthIPTX(Module):
|
|||
|
||||
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
|
||||
fsm.act("IDLE",
|
||||
sink.ack.eq(1),
|
||||
If(sink.stb & sink.sop,
|
||||
sink.ack.eq(0),
|
||||
packetizer.source.ack.eq(1),
|
||||
If(packetizer.source.stb & packetizer.source.sop,
|
||||
packetizer.source.ack.eq(0),
|
||||
NextState("SEND_MAC_ADDRESS_REQUEST")
|
||||
)
|
||||
)
|
||||
self.comb += arp_table.request.ip_address.eq(self.sink.ip_address)
|
||||
self.comb += arp_table.request.ip_address.eq(sink.ip_address)
|
||||
fsm.act("SEND_MAC_ADDRESS_REQUEST",
|
||||
arp_table.request.stb.eq(1),
|
||||
If(arp_table.request.stb & arp_table.request.ack,
|
||||
|
|
@ -99,13 +96,16 @@ class LiteEthIPTX(Module):
|
|||
)
|
||||
)
|
||||
)
|
||||
self.sync += If(arp_table.response.stb, target_mac.eq(arp_table.response.mac_address))
|
||||
self.sync += \
|
||||
If(arp_table.response.stb,
|
||||
target_mac.eq(arp_table.response.mac_address)
|
||||
)
|
||||
fsm.act("SEND",
|
||||
Record.connect(packetizer.source, self.source),
|
||||
self.source.ethernet_type.eq(ethernet_type_ip),
|
||||
self.source.target_mac.eq(target_mac),
|
||||
self.source.sender_mac.eq(mac_address),
|
||||
If(self.source.stb & self.source.eop & self.source.ack,
|
||||
Record.connect(packetizer.source, source),
|
||||
source.ethernet_type.eq(ethernet_type_ip),
|
||||
source.target_mac.eq(target_mac),
|
||||
source.sender_mac.eq(mac_address),
|
||||
If(source.stb & source.eop & source.ack,
|
||||
NextState("IDLE")
|
||||
)
|
||||
)
|
||||
|
|
@ -118,32 +118,29 @@ class LiteEthIPTX(Module):
|
|||
|
||||
class LiteEthIPRX(Module):
|
||||
def __init__(self, mac_address, ip_address):
|
||||
self.sink = Sink(eth_mac_description(8))
|
||||
self.sink = sink = Sink(eth_mac_description(8))
|
||||
self.source = source = Source(eth_ipv4_user_description(8))
|
||||
###
|
||||
depacketizer = LiteEthIPV4Depacketizer()
|
||||
self.submodules += depacketizer
|
||||
self.comb += Record.connect(self.sink, depacketizer.sink)
|
||||
sink = depacketizer.source
|
||||
self.submodules.depacketizer = depacketizer = LiteEthIPV4Depacketizer()
|
||||
self.comb += Record.connect(sink, depacketizer.sink)
|
||||
|
||||
checksum = LiteEthIPV4Checksum(skip_header=False)
|
||||
self.submodules += checksum
|
||||
self.submodules.checksum = checksum = LiteEthIPV4Checksum(skip_checksum=False)
|
||||
self.comb += checksum.header.eq(depacketizer.header)
|
||||
|
||||
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
|
||||
fsm.act("IDLE",
|
||||
sink.ack.eq(1),
|
||||
If(sink.stb & sink.sop,
|
||||
sink.ack.eq(0),
|
||||
depacketizer.source.ack.eq(1),
|
||||
If(depacketizer.source.stb & depacketizer.source.sop,
|
||||
depacketizer.source.ack.eq(0),
|
||||
NextState("CHECK")
|
||||
)
|
||||
)
|
||||
valid = Signal()
|
||||
self.comb += valid.eq(
|
||||
sink.stb &
|
||||
(sink.target_ip == ip_address) &
|
||||
(sink.version == 0x4) &
|
||||
(sink.ihl == 0x5) &
|
||||
depacketizer.source.stb &
|
||||
(depacketizer.source.target_ip == ip_address) &
|
||||
(depacketizer.source.version == 0x4) &
|
||||
(depacketizer.source.ihl == 0x5) &
|
||||
(checksum.value == 0)
|
||||
)
|
||||
|
||||
|
|
@ -155,39 +152,39 @@ class LiteEthIPRX(Module):
|
|||
)
|
||||
)
|
||||
self.comb += [
|
||||
source.sop.eq(sink.sop),
|
||||
source.eop.eq(sink.eop),
|
||||
source.length.eq(sink.total_length - (0x5*4)),
|
||||
source.protocol.eq(sink.protocol),
|
||||
source.ip_address.eq(sink.sender_ip),
|
||||
source.data.eq(sink.data),
|
||||
source.error.eq(sink.error)
|
||||
source.sop.eq(depacketizer.source.sop),
|
||||
source.eop.eq(depacketizer.source.eop),
|
||||
source.length.eq(depacketizer.source.total_length - (0x5*4)),
|
||||
source.protocol.eq(depacketizer.source.protocol),
|
||||
source.ip_address.eq(depacketizer.source.sender_ip),
|
||||
source.data.eq(depacketizer.source.data),
|
||||
source.error.eq(depacketizer.source.error)
|
||||
]
|
||||
fsm.act("PRESENT",
|
||||
source.stb.eq(sink.stb),
|
||||
sink.ack.eq(source.ack),
|
||||
source.stb.eq(depacketizer.source.stb),
|
||||
depacketizer.source.ack.eq(source.ack),
|
||||
If(source.stb & source.eop & source.ack,
|
||||
NextState("IDLE")
|
||||
)
|
||||
)
|
||||
fsm.act("DROP",
|
||||
sink.ack.eq(1),
|
||||
If(sink.stb & sink.eop & sink.ack,
|
||||
depacketizer.source.ack.eq(1),
|
||||
If(depacketizer.source.stb & depacketizer.source.eop & depacketizer.source.ack,
|
||||
NextState("IDLE")
|
||||
)
|
||||
)
|
||||
|
||||
class LiteEthIP(Module):
|
||||
def __init__(self, mac, mac_address, ip_address, arp_table):
|
||||
self.submodules.tx = LiteEthIPTX(mac_address, ip_address, arp_table)
|
||||
self.submodules.rx = LiteEthIPRX(mac_address, ip_address)
|
||||
self.submodules.tx = tx = LiteEthIPTX(mac_address, ip_address, arp_table)
|
||||
self.submodules.rx = rx = LiteEthIPRX(mac_address, ip_address)
|
||||
mac_port = mac.crossbar.get_port(ethernet_type_ip)
|
||||
self.comb += [
|
||||
Record.connect(self.tx.source, mac_port.sink),
|
||||
Record.connect(mac_port.source, self.rx.sink)
|
||||
Record.connect(tx.source, mac_port.sink),
|
||||
Record.connect(mac_port.source, rx.sink)
|
||||
]
|
||||
self.submodules.crossbar = LiteEthIPV4Crossbar()
|
||||
self.submodules.crossbar = crossbar = LiteEthIPV4Crossbar()
|
||||
self.comb += [
|
||||
Record.connect(self.crossbar.master.source, self.tx.sink),
|
||||
Record.connect(self.rx.source, self.crossbar.master.sink)
|
||||
Record.connect(crossbar.master.source, tx.sink),
|
||||
Record.connect(rx.source, crossbar.master.sink)
|
||||
]
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@ class LiteEthIPV4Crossbar(Module):
|
|||
def get_port(self, protocol):
|
||||
port = LiteEthIPV4UserPort(8)
|
||||
if protocol in self.users.keys():
|
||||
raise ValueError("Protocol {} already used".format(protocol))
|
||||
raise ValueError("Protocol {0:#x} already assigned".format(protocol))
|
||||
self.users[protocol] = port
|
||||
return port
|
||||
|
||||
|
|
|
|||
|
|
@ -20,64 +20,60 @@ class LiteEthUDPPacketizer(LiteEthPacketizer):
|
|||
|
||||
class LiteEthUDPTX(Module):
|
||||
def __init__(self, ip_address):
|
||||
self.sink = Sink(eth_udp_user_description(8))
|
||||
self.source = Source(eth_ipv4_user_description(8))
|
||||
self.sink = sink = Sink(eth_udp_user_description(8))
|
||||
self.source = source = Source(eth_ipv4_user_description(8))
|
||||
###
|
||||
packetizer = LiteEthUDPPacketizer()
|
||||
self.submodules += packetizer
|
||||
self.submodules.packetizer = packetizer = LiteEthUDPPacketizer()
|
||||
self.comb += [
|
||||
packetizer.sink.stb.eq(self.sink.stb),
|
||||
packetizer.sink.sop.eq(self.sink.sop),
|
||||
packetizer.sink.eop.eq(self.sink.eop),
|
||||
self.sink.ack.eq(packetizer.sink.ack),
|
||||
packetizer.sink.src_port.eq(self.sink.src_port),
|
||||
packetizer.sink.dst_port.eq(self.sink.dst_port),
|
||||
packetizer.sink.length.eq(self.sink.length + udp_header_len),
|
||||
packetizer.sink.checksum.eq(0),
|
||||
packetizer.sink.data.eq(self.sink.data)
|
||||
packetizer.sink.stb.eq(sink.stb),
|
||||
packetizer.sink.sop.eq(sink.sop),
|
||||
packetizer.sink.eop.eq(sink.eop),
|
||||
sink.ack.eq(packetizer.sink.ack),
|
||||
packetizer.sink.src_port.eq(sink.src_port),
|
||||
packetizer.sink.dst_port.eq(sink.dst_port),
|
||||
packetizer.sink.length.eq(sink.length + udp_header_len),
|
||||
packetizer.sink.checksum.eq(0), # Disabled (MAC CRC is enough)
|
||||
packetizer.sink.data.eq(sink.data)
|
||||
]
|
||||
sink = packetizer.source
|
||||
|
||||
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
|
||||
fsm.act("IDLE",
|
||||
sink.ack.eq(1),
|
||||
If(sink.stb & sink.sop,
|
||||
sink.ack.eq(0),
|
||||
packetizer.source.ack.eq(1),
|
||||
If(packetizer.source.stb & packetizer.source.sop,
|
||||
packetizer.source.ack.eq(0),
|
||||
NextState("SEND")
|
||||
)
|
||||
)
|
||||
fsm.act("SEND",
|
||||
Record.connect(packetizer.source, self.source),
|
||||
self.source.length.eq(packetizer.sink.length),
|
||||
self.source.protocol.eq(udp_protocol),
|
||||
self.source.ip_address.eq(self.sink.ip_address),
|
||||
If(self.source.stb & self.source.eop & self.source.ack,
|
||||
Record.connect(packetizer.source, source),
|
||||
source.length.eq(packetizer.sink.length),
|
||||
source.protocol.eq(udp_protocol),
|
||||
source.ip_address.eq(sink.ip_address),
|
||||
If(source.stb & source.eop & source.ack,
|
||||
NextState("IDLE")
|
||||
)
|
||||
)
|
||||
|
||||
class LiteEthUDPRX(Module):
|
||||
def __init__(self, ip_address):
|
||||
self.sink = Sink(eth_ipv4_user_description(8))
|
||||
self.sink = sink = Sink(eth_ipv4_user_description(8))
|
||||
self.source = source = Source(eth_udp_user_description(8))
|
||||
###
|
||||
depacketizer = LiteEthUDPDepacketizer()
|
||||
self.submodules += depacketizer
|
||||
self.comb += Record.connect(self.sink, depacketizer.sink)
|
||||
sink = depacketizer.source
|
||||
self.submodules.depacketizer = depacketizer = LiteEthUDPDepacketizer()
|
||||
self.comb += Record.connect(sink, depacketizer.sink)
|
||||
|
||||
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
|
||||
fsm.act("IDLE",
|
||||
sink.ack.eq(1),
|
||||
If(sink.stb & sink.sop,
|
||||
sink.ack.eq(0),
|
||||
depacketizer.source.ack.eq(1),
|
||||
If(depacketizer.source.stb & depacketizer.source.sop,
|
||||
depacketizer.source.ack.eq(0),
|
||||
NextState("CHECK")
|
||||
)
|
||||
)
|
||||
valid = Signal()
|
||||
self.comb += valid.eq(
|
||||
sink.stb &
|
||||
(self.sink.protocol == udp_protocol)
|
||||
depacketizer.source.stb &
|
||||
(sink.protocol == udp_protocol)
|
||||
)
|
||||
|
||||
fsm.act("CHECK",
|
||||
|
|
@ -88,43 +84,43 @@ class LiteEthUDPRX(Module):
|
|||
)
|
||||
)
|
||||
self.comb += [
|
||||
source.sop.eq(sink.sop),
|
||||
source.eop.eq(sink.eop),
|
||||
source.src_port.eq(sink.src_port),
|
||||
source.dst_port.eq(sink.dst_port),
|
||||
source.ip_address.eq(self.sink.ip_address),
|
||||
source.length.eq(sink.length - udp_header_len),
|
||||
source.data.eq(sink.data),
|
||||
source.error.eq(sink.error)
|
||||
source.sop.eq(depacketizer.source.sop),
|
||||
source.eop.eq(depacketizer.source.eop),
|
||||
source.src_port.eq(depacketizer.source.src_port),
|
||||
source.dst_port.eq(depacketizer.source.dst_port),
|
||||
source.ip_address.eq(sink.ip_address),
|
||||
source.length.eq(depacketizer.source.length - udp_header_len),
|
||||
source.data.eq(depacketizer.source.data),
|
||||
source.error.eq(depacketizer.source.error)
|
||||
]
|
||||
fsm.act("PRESENT",
|
||||
source.stb.eq(sink.stb),
|
||||
sink.ack.eq(source.ack),
|
||||
source.stb.eq(depacketizer.source.stb),
|
||||
depacketizer.source.ack.eq(source.ack),
|
||||
If(source.stb & source.eop & source.ack,
|
||||
NextState("IDLE")
|
||||
)
|
||||
)
|
||||
fsm.act("DROP",
|
||||
sink.ack.eq(1),
|
||||
If(sink.stb & sink.eop & sink.ack,
|
||||
depacketizer.source.ack.eq(1),
|
||||
If(depacketizer.source.stb & depacketizer.source.eop & depacketizer.source.ack,
|
||||
NextState("IDLE")
|
||||
)
|
||||
)
|
||||
|
||||
class LiteEthUDP(Module):
|
||||
def __init__(self, ip, ip_address, with_loopback):
|
||||
self.submodules.tx = LiteEthUDPTX(ip_address)
|
||||
self.submodules.rx = LiteEthUDPRX(ip_address)
|
||||
self.submodules.tx = tx = LiteEthUDPTX(ip_address)
|
||||
self.submodules.rx = rx = LiteEthUDPRX(ip_address)
|
||||
ip_port = ip.crossbar.get_port(udp_protocol)
|
||||
self.comb += [
|
||||
Record.connect(self.tx.source, ip_port.sink),
|
||||
Record.connect(ip_port.source, self.rx.sink)
|
||||
Record.connect(tx.source, ip_port.sink),
|
||||
Record.connect(ip_port.source, rx.sink)
|
||||
]
|
||||
if with_loopback:
|
||||
self.submodules.fifo = SyncFIFO(eth_udp_user_description(8), 2048, buffered=True)
|
||||
self.submodules.fifo = fifo = SyncFIFO(eth_udp_user_description(8), 2048, buffered=True)
|
||||
self.comb += [
|
||||
Record.connect(self.rx.source, self.fifo.sink),
|
||||
Record.connect(self.fifo.source, self.tx.sink)
|
||||
Record.connect(rx.source, fifo.sink),
|
||||
Record.connect(fifo.source, tx.sink)
|
||||
]
|
||||
else:
|
||||
self.sink, self.source = self.tx.sink, self.rx.source
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@ class LiteEthMACCrossbar(Module):
|
|||
def get_port(self, ethernet_type):
|
||||
port = LiteEthMACUserPort(8)
|
||||
if ethernet_type in self.users.keys():
|
||||
raise ValueError("Ethernet type {} already used".format(ethernet_type))
|
||||
raise ValueError("Ethernet type {0:#x} already assigned".format(ethernet_type))
|
||||
self.users[ethernet_type] = port
|
||||
return port
|
||||
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@ from config import *
|
|||
wb.open()
|
||||
regs = wb.regs
|
||||
###
|
||||
regs.ethphy_crg_reset.write(1)
|
||||
regs.phy_crg_reset.write(1)
|
||||
print("sysid : 0x%04x" %regs.identifier_sysid.read())
|
||||
print("revision : 0x%04x" %regs.identifier_revision.read())
|
||||
print("frequency : %d MHz" %(regs.identifier_frequency.read()/1000000))
|
||||
|
|
|
|||
Loading…
Reference in New Issue