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tools/litex_sim: cleanup cpu endianness.

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Florent Kermarrec 2020-07-01 09:47:10 +02:00
parent 1c631ceeee
commit 996e9a9180
1 changed files with 5 additions and 7 deletions
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12
litex/tools/litex_sim.py
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@ -19,6 +19,7 @@ from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import * from litex.soc.integration.builder import *
from litex.soc.integration.soc import * from litex.soc.integration.soc import *
from litex.soc.cores.bitbang import * from litex.soc.cores.bitbang import *
from litex.soc.cores.cpu import CPUS
from litedram import modules as litedram_modules from litedram import modules as litedram_modules
from litedram.modules import parse_spd_hexdump from litedram.modules import parse_spd_hexdump
@ -346,19 +347,16 @@ def main():
# Configuration -------------------------------------------------------------------------------- # Configuration --------------------------------------------------------------------------------
cpu_endianness = "little" cpu = CPUS[soc_kwargs.get("cpu_type", "vexriscv")]
if "cpu_type" in soc_kwargs:
if soc_kwargs["cpu_type"] in ["mor1kx", "lm32"]:
cpu_endianness = "big"
if soc_kwargs["uart_name"] == "serial": if soc_kwargs["uart_name"] == "serial":
soc_kwargs["uart_name"] = "sim" soc_kwargs["uart_name"] = "sim"
sim_config.add_module("serial2console", "serial") sim_config.add_module("serial2console", "serial")
if args.rom_init: if args.rom_init:
soc_kwargs["integrated_rom_init"] = get_mem_data(args.rom_init, cpu_endianness) soc_kwargs["integrated_rom_init"] = get_mem_data(args.rom_init, cpu.endianness)
if not args.with_sdram: if not args.with_sdram:
soc_kwargs["integrated_main_ram_size"] = 0x10000000 # 256 MB soc_kwargs["integrated_main_ram_size"] = 0x10000000 # 256 MB
if args.ram_init is not None: if args.ram_init is not None:
soc_kwargs["integrated_main_ram_init"] = get_mem_data(args.ram_init, cpu_endianness) soc_kwargs["integrated_main_ram_init"] = get_mem_data(args.ram_init, cpu.endianness)
else: else:
assert args.ram_init is None assert args.ram_init is None
soc_kwargs["integrated_main_ram_size"] = 0x0 soc_kwargs["integrated_main_ram_size"] = 0x0
@ -382,7 +380,7 @@ def main():
with_analyzer = args.with_analyzer, with_analyzer = args.with_analyzer,
with_i2c = args.with_i2c, with_i2c = args.with_i2c,
with_sdcard = args.with_sdcard, with_sdcard = args.with_sdcard,
sdram_init = [] if args.sdram_init is None else get_mem_data(args.sdram_init, cpu_endianness), sdram_init = [] if args.sdram_init is None else get_mem_data(args.sdram_init, cpu.endianness),
**soc_kwargs) **soc_kwargs)
if args.ram_init is not None: if args.ram_init is not None:
soc.add_constant("ROM_BOOT_ADDRESS", 0x40000000) soc.add_constant("ROM_BOOT_ADDRESS", 0x40000000)