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framebuffer: fix FIFO read clocking

This commit is contained in:
Sebastien Bourdeauducq 2012-07-07 11:30:27 +02:00
parent 2dfdc8f3c5
commit 99bb705407
2 changed files with 8 additions and 4 deletions
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3
milkymist/framebuffer/__init__.py
View File

@ -189,6 +189,7 @@ class FIFO(Actor):
return Fragment(
[
asfifo.ins["read_en"].eq(1),
Cat(self.vga_hsync_n, self.vga_vsync_n, self.vga_r, self.vga_g, self.vga_b).eq(asfifo.outs["data_out"]),
self.endpoints["dac"].ack.eq(~asfifo.outs["full"]),
asfifo.ins["write_en"].eq(self.endpoints["dac"].stb),
@ -196,8 +197,6 @@ class FIFO(Actor):
self.busy.eq(0),
asfifo.ins["rst"].eq(0)
], [
Cat(self.vga_hsync_n, self.vga_vsync_n, self.vga_r, self.vga_g, self.vga_b).eq(asfifo.outs["data_out"])
],
instances=[asfifo])

9
verilog/generic/asfifo.v
View File

@ -10,7 +10,7 @@ module asfifo #(
parameter fifo_depth = (1 << address_width)
) (
/* Read port */
output [data_width-1:0] data_out,
output reg [data_width-1:0] data_out,
output reg empty,
input read_en,
input clk_read,
@ -33,7 +33,12 @@ wire set_status, clear_status;
reg status;
wire preset_full, preset_empty;
assign data_out = mem[read_index];
reg [data_width-1:0] data_out0;
always @(posedge clk_read) begin
data_out0 <= mem[read_index];
data_out <= data_out0;
end
always @(posedge clk_write) begin
if(write_en & !full)