storage: simplify run length encoder...
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@ -18,56 +18,44 @@ class RunLengthEncoder(Module, AutoCSR):
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###
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enable = self._r_enable.storage
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stb_i = self.sink.stb
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dat_i = self.sink.dat
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# Register Input
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stb_i_d = Signal()
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dat_i_d = Signal(width)
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fsm = FSM(reset_state="BYPASS")
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self.submodules += fsm
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sink_d = rec_dat(width)
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self.sync += If(self.sink.stb, sink_d.eq(self.sink))
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cnt = Signal(max=length)
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cnt_inc = Signal()
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cnt_reset = Signal()
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cnt_max = Signal()
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self.sync += \
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If(stb_i,
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dat_i_d.eq(dat_i),
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stb_i_d.eq(stb_i)
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If(cnt_reset,
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cnt.eq(1),
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).Elif(cnt_inc,
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cnt.eq(cnt+1)
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)
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self.comb += cnt_max.eq(cnt == length)
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# Detect change
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change = Signal()
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self.comb += change.eq(stb_i & (~enable | (dat_i_d != dat_i)))
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self.comb += change.eq(self.sink.stb & (self.sink.dat != sink_d.dat))
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change_d = Signal()
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change_rising = Signal()
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self.sync += If(stb_i, change_d.eq(change))
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self.comb += change_rising.eq(stb_i & (change & ~change_d))
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# Generate RLE word
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rle_cnt = Signal(max=length)
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rle_max = Signal()
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self.comb += If(rle_cnt == length, rle_max.eq(enable))
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self.sync += \
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If(change | rle_max,
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rle_cnt.eq(0)
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).Else(
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rle_cnt.eq(rle_cnt + 1)
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fsm.act("BYPASS",
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sink_d.connect(self.source),
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cnt_reset.eq(1),
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If(enable & ~change & self.sink.stb, NextState("COUNT"))
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)
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# Mux RLE word and data
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stb_o = self.source.stb
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dat_o = self.source.dat
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self.comb += \
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If(change_rising & ~rle_max,
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stb_o.eq(1),
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dat_o[width-1].eq(1),
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dat_o[:flen(rle_cnt)].eq(rle_cnt)
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).Elif(change_d | rle_max,
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stb_o.eq(stb_i_d),
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dat_o.eq(dat_i_d)
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).Else(
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stb_o.eq(0),
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fsm.act("COUNT",
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cnt_inc.eq(self.sink.stb),
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If(change | cnt_max | ~enable,
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self.source.stb.eq(1),
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self.source.dat[width-1].eq(1), # Set RLE bit
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self.source.dat[:flen(cnt)].eq(cnt),
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NextState("BYPASS")
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)
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),
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class Recorder(Module, AutoCSR):
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def __init__(self, width, depth):
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