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tools/litex_sim: Let the SDRAMPHYModel pick default settings.

This commit is contained in:
Florent Kermarrec 2021-07-08 09:09:57 +02:00
parent fced79631e
commit 9a51dfb50e
1 changed files with 6 additions and 10 deletions
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8
litex/tools/litex_sim.py
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@ -24,9 +24,9 @@ from litex.soc.integration.soc import *
from litex.soc.cores.bitbang import * from litex.soc.cores.bitbang import *
from litex.soc.cores.cpu import CPUS from litex.soc.cores.cpu import CPUS
from litedram import modules as litedram_modules from litedram import modules as litedram_modules
from litedram.modules import parse_spd_hexdump from litedram.modules import parse_spd_hexdump
from litedram.common import *
from litedram.phy.model import sdram_module_nphases, get_sdram_phy_settings from litedram.phy.model import sdram_module_nphases, get_sdram_phy_settings
from litedram.phy.model import SDRAMPHYModel from litedram.phy.model import SDRAMPHYModel
@ -123,13 +123,9 @@ class SimSoC(SoCCore):
sdram_module = sdram_module_cls(sdram_clk_freq, sdram_rate) sdram_module = sdram_module_cls(sdram_clk_freq, sdram_rate)
else: else:
sdram_module = litedram_modules.SDRAMModule.from_spd_data(sdram_spd_data, sdram_clk_freq) sdram_module = litedram_modules.SDRAMModule.from_spd_data(sdram_spd_data, sdram_clk_freq)
phy_settings = get_sdram_phy_settings(
memtype = sdram_module.memtype,
data_width = sdram_data_width,
clk_freq = sdram_clk_freq)
self.submodules.sdrphy = SDRAMPHYModel( self.submodules.sdrphy = SDRAMPHYModel(
module = sdram_module, module = sdram_module,
settings = phy_settings, data_width = sdram_data_width,
clk_freq = sdram_clk_freq, clk_freq = sdram_clk_freq,
verbosity = sdram_verbosity, verbosity = sdram_verbosity,
init = sdram_init) init = sdram_init)