tools/litex_sim: Use automatic ethmac allocation.
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48ec20e2ef
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9a82fd1d54
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@ -153,11 +153,6 @@ def get_sdram_phy_settings(memtype, data_width, clk_freq):
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# Simulation SoC -----------------------------------------------------------------------------------
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# Simulation SoC -----------------------------------------------------------------------------------
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class SimSoC(SoCCore):
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class SimSoC(SoCCore):
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mem_map = {
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"ethmac": 0xb0000000,
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}
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mem_map.update(SoCCore.mem_map)
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def __init__(self,
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def __init__(self,
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with_sdram = False,
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with_sdram = False,
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with_ethernet = False,
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with_ethernet = False,
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@ -234,7 +229,7 @@ class SimSoC(SoCCore):
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hw_mac = etherbone_mac_address)
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hw_mac = etherbone_mac_address)
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# SoftCPU
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# SoftCPU
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self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
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self.add_memory_region("ethmac", self.mem_map.get("ethmac", None), 0x2000, type="io")
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self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000)
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self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000)
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if self.irq.enabled:
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if self.irq.enabled:
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self.irq.add("ethmac", use_loc_if_exists=True)
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self.irq.add("ethmac", use_loc_if_exists=True)
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@ -258,7 +253,7 @@ class SimSoC(SoCCore):
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if with_etherbone:
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if with_etherbone:
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ethmac = ClockDomainsRenamer({"eth_tx": "ethphy_eth_tx", "eth_rx": "ethphy_eth_rx"})(ethmac)
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ethmac = ClockDomainsRenamer({"eth_tx": "ethphy_eth_tx", "eth_rx": "ethphy_eth_rx"})(ethmac)
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self.submodules.ethmac = ethmac
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self.submodules.ethmac = ethmac
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self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
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self.add_memory_region("ethmac", self.mem_map.get("ethmac", None), 0x2000, type="io")
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self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000)
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self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000)
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if self.irq.enabled:
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if self.irq.enabled:
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self.irq.add("ethmac", use_loc_if_exists=True)
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self.irq.add("ethmac", use_loc_if_exists=True)
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