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tools/litex_sim: Use automatic ethmac allocation.

This commit is contained in:
Florent Kermarrec 2021-04-26 18:33:50 +02:00
parent 48ec20e2ef
commit 9a82fd1d54
1 changed files with 2 additions and 7 deletions
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9
litex/tools/litex_sim.py
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@ -153,11 +153,6 @@ def get_sdram_phy_settings(memtype, data_width, clk_freq):
# Simulation SoC -----------------------------------------------------------------------------------
class SimSoC(SoCCore):
mem_map = {
"ethmac": 0xb0000000,
}
mem_map.update(SoCCore.mem_map)
def __init__(self,
with_sdram = False,
with_ethernet = False,
@ -234,7 +229,7 @@ class SimSoC(SoCCore):
hw_mac = etherbone_mac_address)
# SoftCPU
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
self.add_memory_region("ethmac", self.mem_map.get("ethmac", None), 0x2000, type="io")
self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000)
if self.irq.enabled:
self.irq.add("ethmac", use_loc_if_exists=True)
@ -258,7 +253,7 @@ class SimSoC(SoCCore):
if with_etherbone:
ethmac = ClockDomainsRenamer({"eth_tx": "ethphy_eth_tx", "eth_rx": "ethphy_eth_rx"})(ethmac)
self.submodules.ethmac = ethmac
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
self.add_memory_region("ethmac", self.mem_map.get("ethmac", None), 0x2000, type="io")
self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000)
if self.irq.enabled:
self.irq.add("ethmac", use_loc_if_exists=True)