efinix: support PLL, add dbparser and ifacewriter
This commit is contained in:
Franck Jullien
parent
0278d3eee8
commit
9b6ae2ff03
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@ -1 +1,3 @@
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from litex.build.efinix.programmer import EfinixProgrammer
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from litex.build.efinix.dbparser import EfinixDbParser
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from litex.build.efinix.ifacewriter import InterfaceWriter
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@ -0,0 +1,96 @@
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import os
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import csv
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import re
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import xml.etree.ElementTree as et
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namespaces = { 'efxpt' : 'http://www.efinixinc.com/peri_device_db',
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'xi' : 'http://www.w3.org/2001/XInclude'
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}
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class EfinixDbParser():
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def __init__(self, efinity_path, device):
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self.efinity_db_path = efinity_path + '/pt/db/'
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self.device = device
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def get_device_map(self, device):
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with open(self.efinity_db_path + 'devicemap.csv') as f:
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reader = csv.reader(f)
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data = list(reader)
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for d in data:
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if d[0] == device:
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print(d)
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return d
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return None
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def get_package_file_name(self, dmap):
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tree = et.parse(self.efinity_db_path + dmap[2])
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root = tree.getroot()
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inc = root.findall('xi:include', namespaces)
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for i in inc:
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if 'package' in i.get('href'):
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return i.get('href').split('/')[1]
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return None
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def get_die_file_name(self, dmap):
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tree = et.parse(self.efinity_db_path + dmap[2])
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root = tree.getroot()
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inc = root.findall('xi:include', namespaces)
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for i in inc:
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if 'die' in i.get('href'):
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return i.get('href').split('/')[1]
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return None
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def get_pad_name_xml(self, dmap, pin):
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package_file = self.get_package_file_name(dmap)
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tree = et.parse(self.efinity_db_path + 'package/' + package_file)
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root = tree.getroot()
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pm = root.findall('efxpt:package_map', namespaces)
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for p in pm:
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if p.get('package_pin') == pin:
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return (p.get('pad_name'))
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return None
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def get_instance_name_xml(self, dmap, pad):
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die = self.get_die_file_name(dmap)
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tree = et.parse(self.efinity_db_path + 'die/' + die)
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root = tree.getroot()
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ipd = root.find('efxpt:io_pad_definition', namespaces)
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ios = ipd.findall('efxpt:io_pad_map', namespaces)
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for io in ios:
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if io.get('pad_name') == pad:
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return (io.get('instance'))
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return None
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def get_pll_inst_from_gpio_inst(self, dmap, inst):
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die = self.get_die_file_name(dmap)
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tree = et.parse(self.efinity_db_path + 'die/' + die)
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root = tree.getroot()
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peri = root.findall('efxpt:periphery_instance', namespaces)
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for p in peri:
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if p.get('block') == 'pll':
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conn = p.findall('efxpt:single_conn', namespaces)
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for c in conn:
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if c.get('instance') == inst:
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refclk_no = 0
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if c.get('index') == '3':
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refclk_no = 1
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return (p.get('name'), refclk_no)
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return None
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def get_pll_inst_from_pin(self, pin):
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dmap = self.get_device_map(self.device)
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pad = self.get_pad_name_xml(dmap, pin)
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inst = self.get_instance_name_xml(dmap, pad)
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return self.get_pll_inst_from_gpio_inst(dmap, inst)
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@ -25,6 +25,8 @@ from migen.fhdl.namer import build_namespace
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from litex.build.generic_platform import Pins, IOStandard, Misc
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from litex.build import tools
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from litex.build.efinix import InterfaceWriter
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_reserved_keywords = {
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"always", "and", "assign", "automatic", "begin", "buf", "bufif0", "bufif1",
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"case", "casex", "casez", "cell", "cmos", "config", "deassign", "default",
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@ -157,13 +159,16 @@ def _format_conf_constraint(signame, pin, others, resname, fragment, platform):
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fmt_c = [_format_constraint(c, signame, fmt_r, fragment, platform) for c in ([Pins(pin)] + others)]
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return ''.join(fmt_c)
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def _build_iface_conf(named_sc, named_pc, fragment, platform):
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def _build_iface_gpio(named_sc, named_pc, fragment, platform, specials_gpios):
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conf = []
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inst = []
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# GPIO
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for sig, pins, others, resname in named_sc:
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if sig not in specials_gpios:
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inst.append(_create_gpio_instance(fragment, platform, sig, pins))
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else:
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continue
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if len(pins) > 1:
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for i, p in enumerate(pins):
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conf.append(_format_conf_constraint("{}[{}]".format(sig, i), p, others, resname, fragment, platform))
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@ -172,56 +177,20 @@ def _build_iface_conf(named_sc, named_pc, fragment, platform):
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if named_pc:
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conf.append("\n\n".join(named_pc))
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# PLL
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#inst.append()
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conf = inst + conf
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return "\n".join(conf)
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def _build_peri(efinity_path, build_name, partnumber, named_sc, named_pc, fragment, platform):
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def _build_peri(efinity_path, build_name, partnumber, named_sc, named_pc, fragment, platform, additional_iface_commands, specials_gpios):
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pythonpath = ""
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header = "# Autogenerated by LiteX / git: " + tools.get_litex_git_revision()
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header = platform.toolchain.ifacewriter.header(build_name, partnumber)
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gen = platform.toolchain.ifacewriter.generate()
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gpio = _build_iface_gpio(named_sc, named_pc, fragment, platform, specials_gpios)
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add = '\n'.join(additional_iface_commands)
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footer = platform.toolchain.ifacewriter.footer()
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header += """
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import os
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import sys
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home = '{0}'
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os.environ['EFXPT_HOME'] = home + '/pt'
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os.environ['EFXPGM_HOME'] = home + '/pgm'
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os.environ['EFXDBG_HOME'] = home + '/debugger'
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os.environ['EFXIPM_HOME'] = home + '/ipm'
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sys.path.append(home + '/pt/bin')
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sys.path.append(home + '/lib/python3.8/site-packages')
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from api_service.design import DesignAPI
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from api_service.device import DeviceAPI
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is_verbose = {1}
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design = DesignAPI(is_verbose)
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device = DeviceAPI(is_verbose)
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design.create('{2}', '{3}', './../build', overwrite=True)
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"""
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header = header.format(efinity_path, 'True', build_name, partnumber)
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conf = _build_iface_conf(named_sc, named_pc, fragment, platform)
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footer = """
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# Check design, generate constraints and reports
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#design.generate(enable_bitstream=True)
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# Save the configured periphery design
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design.save()
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"""
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tools.write_to_file("iface.py", header + conf + footer)
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tools.write_to_file("iface.py", header + gen + gpio + add + footer)
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subprocess.call([efinity_path + '/bin/python3', 'iface.py'])
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@ -295,6 +264,9 @@ class EfinityToolchain():
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self.efinity_path = efinity_path
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self.additional_sdc_commands = []
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self.additional_xml_commands = []
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self.ifacewriter = InterfaceWriter("iface.py", efinity_path)
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self.specials_gpios = []
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self.additional_iface_commands = []
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def build(self, platform, fragment,
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build_dir = "build",
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@ -319,6 +291,9 @@ class EfinityToolchain():
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v_output.write(v_file)
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platform.add_source(v_file)
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sc = platform.constraint_manager.get_sig_constraints()
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self.specials_gpios = [(v_output.ns.get_name(sig)) for sig in self.specials_gpios]
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if platform.verilog_include_paths:
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self.options['includ_path'] = '{' + ';'.join(platform.verilog_include_paths) + '}'
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@ -349,7 +324,9 @@ class EfinityToolchain():
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named_sc = named_sc,
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named_pc = named_pc,
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fragment = fragment,
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platform = platform)
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platform = platform,
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additional_iface_commands = self.additional_iface_commands,
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specials_gpios = self.specials_gpios)
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# Run
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if run:
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@ -0,0 +1,95 @@
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import os
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from litex.build import tools
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class InterfaceWriter():
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def __init__(self, filename, efinity_path):
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self.file = filename
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self.efinity_path = efinity_path
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self.blocks = []
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def header(self, build_name, partnumber):
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header = "# Autogenerated by LiteX / git: " + tools.get_litex_git_revision()
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header += """
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import os
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import sys
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import pprint
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home = '{0}'
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os.environ['EFXPT_HOME'] = home + '/pt'
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os.environ['EFXPGM_HOME'] = home + '/pgm'
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os.environ['EFXDBG_HOME'] = home + '/debugger'
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os.environ['EFXIPM_HOME'] = home + '/ipm'
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sys.path.append(home + '/pt/bin')
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sys.path.append(home + '/lib/python3.8/site-packages')
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from api_service.design import DesignAPI
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from api_service.device import DeviceAPI
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is_verbose = {1}
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design = DesignAPI(is_verbose)
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device = DeviceAPI(is_verbose)
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design.create('{2}', '{3}', './../build', overwrite=True)
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"""
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return header.format(self.efinity_path, 'True', build_name, partnumber)
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def get_block(self, name):
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for b in self.blocks:
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if b['name'] == name:
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return b
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return None
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def generate_pll(self, block, verbose=True):
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name = block['name']
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cmd = '# ---------- PLL {} ---------\n'.format(name)
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cmd += 'design.create_block("{}", block_type="PLL")\n'.format(name)
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cmd += 'design.gen_pll_ref_clock("{}", pll_res="{}", refclk_src="{}", refclk_name="{}", ext_refclk_no="{}")\n\n' \
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.format(name, block['resource'], block['input_clock'], block['input_clock_name'], block['clock_no'])
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cmd += 'pll_config = {{ "REFCLK_FREQ":"{}" }}\n'.format(block['input_freq'] / 1e6)
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cmd += 'design.set_property("{}", pll_config, block_type="PLL")\n\n'.format(name)
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# Output clock 0 is enabled by default
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for i, clock in enumerate(block['clk_out']):
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if i > 0:
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cmd += 'pll_config = {{ "CLKOUT{}_EN":"1", "CLKOUT{}_PIN":"{}" }}\n'.format(i, i, clock[0])
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cmd += 'design.set_property("{}", pll_config, block_type="PLL")\n\n'.format(name)
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cmd += 'target_freq = {\n'
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for i, clock in enumerate(block['clk_out']):
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cmd += ' "CLKOUT{}_FREQ": "{}",\n'.format(i, clock[1] / 1e6)
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cmd += ' "CLKOUT{}_PHASE": "{}",\n'.format(i, clock[2])
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cmd += '}\n'
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cmd += 'calc_result = design.auto_calc_pll_clock("{}", target_freq)\n\n'.format(name)
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if verbose:
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cmd += 'print("#### {} ####")\n'.format(name)
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cmd += 'clksrc_info = design.trace_ref_clock("{}", block_type="PLL")\n'.format(name)
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cmd += 'pprint.pprint(clksrc_info)\n'
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cmd += 'clock_source_prop = ["REFCLK_SOURCE", "EXT_CLK", "CLKOUT0_EN", "CLKOUT1_EN","REFCLK_FREQ", "RESOURCE"]\n'
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cmd += 'clock_source_prop += ["M", "N", "O", "CLKOUT0_DIV", "CLKOUT2_DIV", "VCO_FREQ", "PLL_FREQ"]\n'
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cmd += 'prop_map = design.get_property("{}", clock_source_prop, block_type="PLL")\n'.format(name)
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cmd += 'pprint.pprint(prop_map)\n'
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cmd += '# ---------- END PLL {} ---------\n\n'.format(name)
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return cmd
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def generate(self):
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output = ''
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for b in self.blocks:
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if b['type'] == 'PLL':
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output += self.generate_pll(b)
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return output
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def footer(self):
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return """
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# Check design, generate constraints and reports
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#design.generate(enable_bitstream=True)
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# Save the configured periphery design
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design.save()"""
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@ -50,3 +50,20 @@ class EfinixPlatform(GenericPlatform):
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if hasattr(to, "p"):
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to = to.p
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self.toolchain.add_false_path_constraint(self, from_, to)
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# TODO: fix this when pin is like p = platform.request("sdios")
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# get_pin_location(p[1])
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# not tested with subsignal like get_pin_location(p.clk)
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def get_pin_location(self, sig):
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sc = self.constraint_manager.get_sig_constraints()
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for s, pins, others, resource in sc:
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if s == sig:
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return pins[0]
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return None
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def get_pin_name(self, sig):
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sc = self.constraint_manager.get_sig_constraints()
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for s, pins, others, resource in sc:
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if s == sig:
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return resource[0]
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return None
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@ -14,3 +14,6 @@ from litex.soc.cores.clock.intel_cyclone10 import Cyclone10LPPLL
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from litex.soc.cores.clock.lattice_ice40 import iCE40PLL
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from litex.soc.cores.clock.lattice_ecp5 import ECP5PLL
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from litex.soc.cores.clock.lattice_nx import NXOSCA, NXPLL
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# Efinix
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from litex.soc.cores.clock.efinix_trion import TRIONPLL
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@ -0,0 +1,92 @@
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#
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# This file is part of LiteX.
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#
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# Copyright (c) 2021 Franck Jullien <franck.jullien@collshade.fr>
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# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.build.generic_platform import *
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from litex.soc.cores.clock.common import *
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from litex.build.efinix import EfinixDbParser
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class Open(Signal): pass
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#TODO: do somthing else
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count = 0
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# Efinix / TRIONPLL ----------------------------------------------------------------------------------
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class TRIONPLL(Module):
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nclkouts_max = 4
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def __init__(self, platform):
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global count
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self.logger = logging.getLogger("TRIONPLL")
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self.logger.info("Creating TRIONPLL.".format())
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self.platform = platform
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self.nclkouts = 0
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self.pll_name = "pll{}".format(count)
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block = {}
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count += 1
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block['type'] = 'PLL'
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block['name'] = self.pll_name
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block['clk_out'] = []
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self.platform.toolchain.ifacewriter.blocks.append(block)
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def register_clkin(self, clkin, freq):
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block = self.platform.toolchain.ifacewriter.get_block(self.pll_name)
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# If clkin has resource, PLL clock input is EXTERNAL
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# When PLL clock is external, it must not be present in the top file
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# Add a test on clkin resource here
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block['input_clock_name'] = self.platform.get_pin_name(clkin)
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pin_name = self.platform.get_pin_location(clkin)
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self.platform.delete(clkin)
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#tpl = "create_clock -name {clk} -period {period} [get_ports {{{clk}}}]"
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#sdc = self.platform.toolchain.additional_sdc_commands
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#sdc.append(tpl.format(clk=block['input_clock_name'], period=1/freq))
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parser = EfinixDbParser(self.platform.efinity_path, self.platform.device)
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(pll_res, clock_no) = parser.get_pll_inst_from_pin(pin_name)
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block['input_clock'] = 'EXTERNAL'
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block['input_freq'] = freq
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block['resource'] = pll_res
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block['clock_no'] = clock_no
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self.logger.info("Using {}".format(pll_res))
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self.logger.info("Clock source: {}, using EXT_CLK{}".format(block['input_clock'], clock_no))
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def create_clkout(self, cd, freq, phase=0, margin=1e-2, with_reset=True):
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assert self.nclkouts < self.nclkouts_max
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clk_out_name = '{}_CLKOUT{}'.format(self.pll_name, self.nclkouts)
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self.platform.add_extension([(clk_out_name, 0, Pins(1))])
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tmp = self.platform.request(clk_out_name)
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# We don't want this IO to be in the interface configuration file as a simple GPIO
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self.platform.toolchain.specials_gpios.append(tmp)
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self.comb += cd.clk.eq(tmp)
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create_clkout_log(self.logger, cd.name, freq, margin, self.nclkouts)
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self.nclkouts += 1
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|
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block = self.platform.toolchain.ifacewriter.get_block(self.pll_name)
|
||||
block['clk_out'].append([clk_out_name, freq, phase, margin])
|
||||
|
||||
def compute_config(self):
|
||||
pass
|
||||
|
||||
def set_configuration(self):
|
||||
pass
|
||||
|
||||
def do_finalize(self):
|
||||
pass
|
||||
Loading…
Reference in New Issue